The Evolution of Transistors from Planar FETs to MBCFETs™

The chip manufacturing process has moved from the micron level to the 2nm era, and the transistor architecture has undergone four key evolutions from Planar FET to MBCFET™. It's not just a change of shape, it's a challenge to the limits of physics. From planar transistors to MBCFETs™, what physical bottlenecks have been solved by each architecture evolution?

The original Planar FETs were two-dimensional planar structures, also known as planar field-effect transistors. Its structure is simple: the electronic channel is "lying down" on the surface of the silicon wafer, while the gate is covered above the channel, and the entire current flow is carried out horizontally on the surface of the wafer.

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This design was born in the 60s of the last century and quickly became mainstream. It formed the basis of the first generation of LSIs and performed very well and was very mature in manufacturing at the process nodes above 90 nanometers. But the problem arises after the process continues to be scaled up. Especially below 28 nanometers, the short channel effect begins to intensify, the gate's control over the channel becomes weaker and weaker, and the transistor is like a "clean faucet", and the leakage current continues to rise. The result: higher power consumption, increased heat generation, and increasingly severe performance bottlenecks.

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So, in 2011, Intel took the lead in introducing the next generation of transistor architecture, FinFET, also known as fin field-effect transistor. Its structure looks like the fins of a fish, hence the name FinFET.

You can think of it as turning an electron channel that used to "lie flat on the ground" into a fin, and the gate no longer just covers the top, but wraps the channel from both sides or even three sides.

This three-dimensional structure, which uses a fin-like 3D structure to increase the contact area, greatly enhances the gate's ability to control the electrons. The result: less leakage, less power consumption, the ability to shrink transistors, and Moore's Law continues.

But FinFETs are not without their limitations. As the process approached 5nm, it also hit a bottleneck. The most important thing is that the fin width is fixed and cannot be adjusted flexibly. However, when we tried to make the fins thinner and smaller to accommodate more advanced processes, the manufacturing difficulty increased dramatically, and yield, reliability, and consistency began to be challenged. In other words, the "fins" of FinFETs have become too thin and brittle to withstand the complexity of future nanoscale scaling.

Therefore, GAAFET came into being in this context. The biggest difference with FinFETs is that GAAFET turns the channel into a very thin nanowire and then has the gate wrap it completely from all four sides – top, bottom, left and right. In this way, the gate has a stronger ability to control the current, and almost 360 degrees of electric field control without dead angles is achieved. This allows the transistor to "turn off" even at a smaller size, dramatically reducing leakage current, making it ideal for sub-5nm process nodes.

However, although GAAFET's "nanowires" are well controlled, they are also too thin and have a weak ability to pass current, which is not conducive to the current drive of high-performance chips, limiting its performance in some high-frequency or high-load scenarios.

As a result, a new generation of structures was proposed – MBCFETs™, also known as multi-bridge channel transistors.

The core idea is to "flatten" the nanowires into layers of "nanosheets", and then stack them horizontally to form multiple channels like building blocks. Each layer of nanosheets is surrounded by a gate, which not only retains the strong control ability of GAA, but also further improves the conductivity and drive current.

What's more, the channel width of MBCFETs™ is adjustable, allowing for flexible trade-offs between performance and power consumption based on design needs, which is not possible with FinFETs.