Chip Manufacturing: Copper

On chips the size of fingernails, tens of billions of transistors need to be connected by metal wires a thousand times thinner than a human hair. By the time the process reaches the 130nm node, traditional aluminum interconnects are no longer sufficient – and the introduction of copper (Cu) is like a nanoscale "metal revolution", making a qualitative leap in chip performance and energy efficiency.

 

1. Why copper? --The three major dilemmas of aluminum interconnection

Aluminum (Al) dominated the interconnect space for 30 years before IBM first introduced copper to chip manufacturing in 1997, but the nano era exposed its fatal flaws:

Characteristic	Al	Cu	Advantage Improving
Resistivity	2.65 μΩ·cm	1.68 μΩ·cm	Decrease37%
Resistance to electromigration	Failure current density<1 MA/cm²	>5 MA/cm²	5x improvement
Coefficient of thermal expansion	23 ppm/℃	17 ppm/℃	Better match for silicon substrates

Aluminum's rout: In the 130 nm node, the aluminum wire resistor accounts for 70% of the RC delay, and the chip frequency is stuck at 1 GHz; At a current density of > 10⁶ A/cm², the aluminum atoms are "blown away" by electrons and the wires break.

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II. The Secret of Copper Interconnects: The Double Damascus Process

Copper could not be etched directly, and engineers invented the double Damascus process(Dual Damascene)：

Process(Take the 5 nm node as an example)：

1. Dielectric layer notching：

Photolithography on Low-k material, etching out wire grooves and vias);

2. Atomic-level protection：

deposition of a 2 nm tantalum (Ta) barrier layer (copper diffusion resistance); deposition of 1 nm ruthenium (Ru) seed layer (enhanced adhesion);

3. Super-filled plating：

Energized in copper plating solution (CuSO₄ + additives) for bottom-up filling;

4. Chemical mechanical polishing：

Two-step polishing: first grinding the copper layer, then polishing the barrier layer, the surface undulation < 0.3 nm.

III,The central role of copper in chips

1. Globally interconnected "galvanic arteries"

High-layer thick copper wire (M8-M10 layer): thickness 1-3 μm, transmission clock/power signal (current>10 mA); The grain > 1 μm after annealing at 1100°C.

2. Locally interconnected "nanowires"

Low-layer copper wires (M1-M3 layers): 10-20 nm line width, connecting adjacent transistors; Cobalt-encapsulated copper technology inhibits electromigration.

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3. Three-dimensional stacked "vertical elevators"

Through-silicon vias (TSV): copper pillars with a diameter of 5 μm and a depth of 100 μm connect the upper and lower chips; Thermal expansion matching design to avoid stress cracking.