Back-end interconnects of four types of chips: the process logic behind the differences in the number of layers

In chip manufacturing, the back-end interconnect (BEOL) is responsible for connecting the underlying transistors into complete circuits. The number of metal layers and material choices vary greatly between different chips, determined by their respective application requirements.
Logic chips

(CPU/GPU) have the highest interconnect requirements. They need to connect billions of transistors into complex high-speed paths, including densely packed local signal lines, as well as wide power lines and global buses. Therefore, logic chips have the most metal layers, with advanced nodes (such as 5nm and 3nm) typically having 12 to 16 layers. The bottom layers use copper and low-k dielectrics, with fine linewidths and high density; the middle layers carry global signals; and the top layer, a thick metal layer, is used for power supply and heat dissipation.

DRAM memory

The goal is to achieve high storage density and fast access speed. Its cell structure is regular, the peripheral circuitry is relatively simple, and the interconnect complexity is lower than that of logic. Mainstream DRAMs have between 3 and 6 metal layers, generally using copper interconnects, but do not require extremely low-k dielectrics because latency is not the primary bottleneck.

NAND flash memory

(Especially 3D NAND) memory cells are stacked vertically at the bottom, with peripheral circuitry on the sides or top. Its interconnects primarily connect the peripheral logic and word lines/bit lines, with fewer layers than logic layers, typically 4 to 8. Since memory density relies mainly on vertical stacking, fewer metal layers are needed, but the thickness and width of each metal layer are optimized according to the current load.

power chip

The task of power chips (such as MOSFETs, IGBTs, and GaN HEMTs) is to carry high currents and withstand high voltages. They have a small number of transistors (usually only one or a few power transistors), and the interconnects are very simple. Power chips typically have only one or two metal layers, and the metal is very thick (several micrometers or even tens of micrometers) to reduce resistance and withstand high currents. The materials used are mostly aluminum or copper, and sometimes a thick layer of aluminum or electroplated copper is deposited on the top layer.

Why these differences? Logic chips need to process massive amounts of signals, requiring multi-layered fine lines to achieve high-density wiring; memory chips focus on cell density and access bandwidth, with moderate interconnects; power devices emphasize low resistance and high reliability, erring on the side of thickness rather than quantity. Furthermore, cost is also a significant factor-each additional metal layer adds a photolithography and deposition process, causing costs to rise sharply. Therefore, engineers precisely select the number of metal layers and process scheme based on the actual needs of the chip, finding the optimal balance between performance, power consumption, and cost.