CP yield test

CP (Chip Probing) refers to wafer testing. CP testing occurs between wafer fabrication and packaging in the entire chip manufacturing process. After the wafer is fabricated, thousands of bare dies (unpackaged chips) are regularly distributed throughout the wafer. Since dicing and packaging have not yet been performed, all the chip pins are exposed. These extremely small pins need to be connected to the tester using finer probes.

The purpose of CP testing is to screen out defective products (wafer sort) before packaging, thereby improving the yield rate and reducing the cost of subsequent packaging and testing.

During chip packaging, some pins are typically encapsulated internally, preventing certain functions from being tested after packaging and requiring testing during the chip development process (CP). Furthermore, some companies categorize chips into multiple performance levels based on CP test results. For example, it's widely believed that Intel CPUs originate from the same wafer, but are sorted according to different product levels and released to different markets.

As mentioned earlier, a chip die will have multiple external pads after the passivation layer, but the final chip will often not utilize all of these pads for external connections.

Some of these pins will be used specifically for CP testing.

The equipment and materials required for CP testing are relatively simple, mainly the testing equipment (including the testing program) and probe cards.

ATE test bench

ATE (Automatic Test Equipment) consists of a tester, loadboard, probe card, handler, and test software. CP testing ATE does not require a loadboard or handler. Currently, manufacturers such as Teradyne and Advantester are available on the market.

probe card

It includes probes and peripheral circuitry. The bare die covers the entire wafer, and each die in the same product batch has a fixed position, thus fixing the chip pin positions. These position coordinates and spacing are determined before chip production (similar to the step calculations in photolithography).

Probes are made of materials such as tungsten copper, beryllium copper, or palladium, each with its own characteristics in terms of strength, conductivity, lifespan, and cost. The probe card also needs to have its site count determined. Increasing the site count can save on testing time costs, but due to limitations in testing equipment resources, there is an upper limit to the site count, such as 32/16/8/4.

During testing, the wafer is loaded onto the test platform, and probe cards are attached to the test pads. Electrical signals are applied between different pins to perform different tests.
The CP testing process mainly includes the following steps:
1) Wafer Incoming Inspection:
This step checks the quality of wafers shipped from the fab, including surface defects and other wafer defects. Wafers that do not meet standards are contacted with the wafer owner (design house or IDM) for handling.
2) CP Testing

CP testing typically includes testing of digital and analog circuits, as well as mixed-signal circuits. The scope of testing is broad, ranging from basic electrical parameter testing to complex functional and performance testing.

Device parameters include Vt threshold voltage, Rdson on-resistance, BVdss source-drain breakdown voltage, and Igss gate-source leakage current.

Functional testing will be conducted at a more complex level of functional blocks or at the entire chip level, such as SCAN to check chip logic functions, SRAM storage function testing, ROM storage function testing, and specific function testing.

It should be noted that the cost of CP testing (especially after mass production) is mainly related to the testing time, so test engineers should also try to find ways to increase the number of projects tested at the same time.

Furthermore, some chips with simple structures and functions may skip the CP testing stage and proceed directly to FT testing after packaging for cost reasons. Therefore, CP testing is better, not necessary.

Only when the design is guaranteed to be sound and the WAT (Design Assessment Test) meets the standards can the risk of blind sealing be taken. Otherwise, it is best to complete the CP (Content Testing) test before the FT (Failure Testing) test.

3) Data inspection

In CP testing, various types of test failures may occur, and they will be numbered according to certain rules, such as Bin 2~N; while tests that pass will also be numbered, generally as Bin 1. Different testing facilities or design houses may use different coding rules.

Different bins are plotted according to the die's position, thus obtaining CP Mapping:

Green represents the Pass Bin, and the other different colors represent different Fail Bins.

0020-42287 PLATE PERF 8INCH EC WXZ