TSV-based Three-dimensional Integrated Circuits

The core goal of 3D integrated circuit technology is to break through the physical limit of 2D by vertically stacking chips, and at the same time meet the comprehensive requirements of high density, high performance, high reliability and low cost.

To achieve this, the process needs to focus on the optimization of through-silicon via (TSV) technology, including the use of tiny-diameter TSV arrays to minimize chip area and increase data transmission bandwidth, while reducing TSV height and parasitic capacitance to meet the needs of high-speed and low-power devices. In addition, thermal management design is required to enhance heat dissipation capacity to ensure thermodynamic and electrical stability, and ensure the compatibility of the three-dimensional integrated process to the front-end and back-end processes (FEOL/BEOL) to reduce process disturbances.

The typical copper (Cu) TSV manufacturing process covers through-hole etching, insulation layer deposition, adhesion layer and diffusion barrier layer deposition, seed layer preparation and electroplating filled copper materials, and then needs to combine silicon wafer thinning, high-precision alignment and bonding technology to complete multi-layer chip interconnection. Ultimately, wafer-level bonding, known good chip (KGD) screening, and heterogeneous die stacking strategies require a process that balances performance, yield, and cost to promote the evolution of 3D integration technology to large-scale applications.

This article mainly introduces the relevant knowledge of TSV-based 3D integrated circuits, which are described as follows:

TSV manufacturing sequence classification and process characteristics

Three-dimensional integrated circuit stacking method

Three-dimensional integrated circuit bonding

TSV manufacturing sequence classification and process characteristics

According to the position of TSV (through-silicon via) in the integrated circuit process, its manufacturing sequence can be divided into three categories: Via First, Via Middle, and Via Last. The following are the core differences and key technical points of the three types of processes:

1. Via First

Process sequence: TSV is manufactured before the CMOS front-end process (FEOL), that is, TSV etching, insulation layer deposition, and conductive material filling (such as polysilicon or tungsten) are completed on a blank silicon wafer, and then transistors and interconnect layers are fabricated.

Core features: Material selection: It needs to withstand high temperatures above 1000°C (such as polysilicon, tungsten) to avoid damage to the TSV structure in the subsequent CMOS process.

Connection: The TSV is interconnected with the first layer of metal (M1) through a tungsten plug, and the adjacent layer of TSV cannot be directly bonded, so it needs to be transitioned by a planar interconnection layer.

Advantages: Simplified process (no need for diffusion barrier/seed layer), good thermal matching (polysilicon CTE is close to silicon), support for high aspect ratio TSV (above 20:1).

Limitations: high resistivity (polysilicon/tungsten resistance is much higher than copper), large TSV diameter (1~5μm), limited flexibility.

2. Via Middle Process

Process sequence: TSV is manufactured after the CMOS front-end process (FEOL) is completed and the back-end process (BEOL) is completed, that is, the TSV is inserted after the transistor is manufactured and the TSV is inserted before the multi-layer interconnect.

Key features:

Material selection: Copper (Cu) filling is preferred, with excellent electrical properties (low resistance, low parasitic capacitance), but a complex diffusion barrier layer is required to prevent copper contamination.

Connection: The TSV is directly interconnected with the M1 layer, which provides high design flexibility, but requires an optimized CMP process (high selectivity to remove copper without damaging the tungsten plug).

Advantages: Compatible with standard CMOS process, TSV aspect ratio is uniform, supports high-layer metal connections (such as Mn), and is suitable for high-performance requirements.

Limitations: The coefficient of thermal expansion (CTE) of copper is very different from that of silicon, which is easy to cause thermal stress. TSV etching needs to avoid the metal layer, and there are many design constraints.

3. Via Last Process

Process sequence: TSV is manufactured after the completion of the CMOS post-process (BEOL), which is divided into two sub-categories: pre-bonding and post-bonding:

Bonding the front and rear vias: After BEOL is completed, the TSV is fabricated, and then the chip is bonded and downgauged.

Post-bonding via vias: Thin wafers are bonded before TSVs are fabricated and interlayer connections are achieved by electroplating or hot press bonding.

Key features:

Material selection: Copper is the mainstream filler material, which supports TSV direct bonding (such as Cu-Cu hot pressing bonding) and has high connection strength.

Connection: TSVs can be directly connected across layers (e.g., Mn to Mn), but need to solve dielectric layer etching challenges (e.g., lateral broadening of low-k materials).

Advantages: TSV is flexible in location, supports heterogeneous chip stacking, and is suitable for high-density integration.

Limitations: The etching process is complex (needs to penetrate multiple layers of dielectric/silicon), and the CMP needs to be compatible with the final metal layer, which is costly.

4. Process comparison and selection basis

Performance priority: Medium through-hole (copper TSV) is suitable for high-speed and low-power scenarios; First through via (polysilicon/tungsten) is suitable for high-temperature process compatibility.

Cost-sensitive: The through-hole process can be prefabricated by wafer manufacturers to reduce packaging costs. The rear through hole needs to be etched complexly, and the cost is high.

Design flexibility: The mid-via supports high-rise metal connections, and the rear vias enable direct bonding across layers, while the first vias are limited to a fixed position.

Reliability: The thermal stress of the first through hole is low, the copper diffusion problem needs to be solved in the middle through hole, and the second through hole needs to optimize the etching damage of the dielectric layer. The three types of processes have their own advantages and disadvantages, and they need to be comprehensively selected according to product requirements.

Three-dimensional integrated circuit bonding

In 3D integrated circuits, the stacking method of chip-to-chip bonding directly affects the interconnection density, heat dissipation performance, and process complexity, and is mainly divided into two modes: front-to-front (F2F) and front-to-back (F2B).

1. Front-to-face (F2F) stacking

Structural features: The upper chip is flipped face down, and the front of the lower chip is directly bonded, and the device layer is placed opposite each other.

High-density interconnects: In addition to TSVs, the upper and lower chips can be directly bonded by metal bumps, allowing the number of interconnects to exceed TSV limits, simplifying the process and improving reliability.

Process flexibility: The upper die can be bonded prior to downgauging without the need for secondary disc support.

Main limitations:

Thermal challenges: The device has a small layer spacing and high heat density after integration, so the heat dissipation design needs to be strengthened.

Limited multi-layer expansion: If the stack exceeds two layers, the upper chip needs to be converted to F2B mode, and the metal bump interconnection cannot be continuously utilized.

2. Front-to-back (F2B) stacking

Structural features: The upper chip is kept facing up, and the lower chip is bonded through the back, and the device layers are arranged sequentially.

Core Benefits: Heat Drain Optimization: The silicon substrate is located between two device layers to enhance heat dissipation.

Multi-layer compatibility: The process flow can be repeatedly expanded, and it is naturally suitable for stacking chips with three or more layers.

Main limitations: Process complexity: The upper chip needs to be thinned in advance, and the disc needs to be assisted to prevent bending and deformation. The interconnect relies on TSV: The interlayer interconnection is completely determined by the number of TSVs, and it is difficult to achieve the bump-level interconnection density of F2F.

3. Stacking method selection basis

Two-layer stacking-first F2F: Maximize the use of metal bump interconnects, reduce costs, and streamline processes.

Mandatory F2B for three layers and above: ensures process scalability, but can be combined with hybrid modes (e.g., F2F for the first and last layers, F2B for the middle layer).

Functional requirements-driven: Specific applications (e.g., sensors, optoelectronic integration) may require a fixed orientation, and the stacking method needs to be selected according to the functional design.

F2F excels at interconnect density and process simplicity, making it suitable for two-layer stacking; F2B dominates complex integrations through thermal optimization and multi-layer compatibility, which can be flexibly combined to balance performance and cost.

Three-dimensional integrated circuit bonding

In the manufacturing of 3D integrated circuits, the choice of bonding method directly affects the yield, cost and process efficiency, which are mainly divided into three modes: chip-to-chip (D2D), chip-to-wafer (D2W) and wafer-to-wafer (W2W).

Chip-to-chip (D2D) bonding

Core features: a single chip is directly bonded to a single chip.

Advantage:

Yield optimization: Failed chips can be rejected before bonding, so as to avoid low yield chips affecting the overall yield.

High flexibility: Adapt to the stacking of chips of different sizes to reduce the waste of small-size chips.

Limitations:

Low efficiency: time-consuming chip-by-chip bonding, limited alignment accuracy (usually 5~10μm). Cost-sensitive: suitable for small batches or high-value chips, large-scale production efficiency is insufficient.

Chip-to-wafer (D2W) bonding

Core features: A single chip is bonded to a complete wafer.

Advantage:

Improved efficiency: Chips are repeatedly bonded after the wafer is fixed, reducing loading time.

Yield control: Both wafers and chips can be pre-tested, skipping failure areas to reduce costs.

Limitations:

Thermal stress risk: Chips and bonded chips need to undergo multiple high-temperature processes, which challenges reliability.

Complex process: Precise control of the coefficient of thermal expansion (CTE) between the chip and the wafer is required.

3. Wafer-to-wafer (W2W) bonding

Core features: one-time bonding of complete wafers and complete wafers. Advantages:

Highest efficiency: Full wafer bonding in a single alignment, suitable for mass production.

Less thermal process: Only one high-temperature process is required, and the risk of thermal stress is low.

Limitations:

Yield risk: Failure to pre-reject failed chips will lead to a surge in overall costs due to low single-layer yield.

Size limit: The size of the upper and lower discs is required to be strictly matched, otherwise the area will be wasted.

4. Bonding method selection strategy

D2D application scenarios: The yield of stacked chips fluctuates greatly, the size difference is significant, or customized low-volume production is required.

D2W Balanced Choice: Balanced efficiency and yield control, suitable for medium-scale production and scenarios with strict thermal management requirements.

W2W efficiency priority: Only used when the wafer size is matched and the yield is very high (e.g., ≥99%), commonly found in homogeneous chip stacks (e.g., memory cubes).

The choice of bonding method should be based on cost, yield, thermal stability, and dimensional compatibility. In small-size chips or high-yield scenarios, W2W can significantly reduce costs. In complex heterogeneous integration or yield-sensitive scenarios, the flexibility of D2D or D2W is even more critical.