Introduction To MOS Tubes And Intrinsic Gains

MOS, which is the abbreviation of the English name of metal-oxide-semiconductor field-effect transistor, is a unique semiconductor device that controls the current of the output loop through the electric field effect, which gives it its name. The device relies primarily on the majority of carriers in semiconductors to conduct electricity, so it is also classified as a unipolar transistor. In addition to MOS transistors, there are various types such as junction FETs (JFETs), metal-semiconductor FETs, JLFETs, and QWFETs. Among these types, MOS transistors are the most commonly used choice due to their many advantages, such as high input resistance, low power consumption, low noise, and ease of integration, and are widely used in analog and digital circuits, and occupy an absolute dominant position in the market, far exceeding bipolar transistors (BJTs).

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MOS transistors are further subdivided into NMOS (N-channel type) and PMOS (P-channel type), both of which belong to insulated gate FETs. When NMOS and PMOS are cleverly combined, they form what we often call CMOS (Complementary Metal-Oxide-Semiconductor) devices. The structure of NMOS is designed to be exquisite, including three key electrodes: Source (S), Gate (G), and Drain (D), which can be functionally correlated to the emitter, base, and collector of a bipolar transistor, respectively, as shown in the figure below.

Schematic diagram of NMOS structure

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As shown in the figure below, if no voltage is applied to the gate during the operation of NMOS, the current cannot be formed between the source and drain regions due to the lack of conductive channels. However, when a sufficiently large positive voltage is applied to the gate, this voltage acts like a magnet to attract a small number of carriers-electrons-in the P-type substrate, causing them to concentrate at the junction of the gate and substrate. With the accumulation of electrons, an inverse layer full of electrons will be formed on the surface of the substrate, which actually inverts the original P-type region into an N-type region, thus providing a smooth channel for the current, so that the electrons in the source region can flow smoothly to the drain region to form a current. This process demonstrates the essence of the MOS transistor as a voltage control device, i.e., the gate voltage is used to precisely regulate the current between the source and drain. This inverse layer creates an efficient electron transport path, which allows electrons in the source region to flow continuously to the drain region, resulting in the formation of an electric current. Therefore, the MOS transistor is essentially a voltage control device, the core of which is to precisely control the current between the source and drain through the gate voltage. We define the minimum gate voltage necessary to turn on the FET as the threshold voltage. The gate plays the role of a switch here: when the gate voltage falls below the threshold voltage or when the gate voltage is removed, it is turned off, preventing the passage of current between source and drain; When the gate voltage is above the threshold voltage, it opens the channel and allows the current between source and drain to flow freely.

Electrical properties of NMOS
Next, we outline a typical NMOS tube preparation process. First, an epitaxial layer is formed on a silicon substrate by epitaxial growth, this step aims to obtain a silicon single crystal with low oxygen content, which constitutes the semiconductor moiety (S) of the MOS tube, and then the field oxide is prepared by oxidation, photolithography and etching techniques, which is used to isolate the different MOS tubes and prevent electrical interference between them. Next, an oxidation process is passed to generate a gate oxide layer, which is the oxide moiety (O) in the MOS tube. The next step is to deposit the polysilicon material and form a polysilicon gate through photolithography and etching processes, although polysilicon is not a metal in the traditional sense, it has good conductivity after doping and is suitable for integrated circuit processes, thus replacing the earlier metallic aluminum materials. Then, it enters the production stage of the source zone and the leak zone, which is first windowed by the photolithography process, followed by the injection of phosphorus ions, and annealed to stabilize the structure. This is followed by the deposition of a layer of phosphosilicate glass (PSG) as a dielectric layer, which is smoothed by deposition and reflow processes, laying a good foundation for subsequent lithography steps. The PSG is then photolithography and etching to create the desired pattern. Next, the aluminum-silicon alloy is deposited as the metal connection material, and the metal connection is prepared by photolithography and etching processes. Finally, a layer of silicon nitride is deposited as a passivation protective layer to provide additional protection and stability to the entire device.

Intrinsic gain of the MOS tube
The maximum low-frequency small-signal gain that a transistor can exhibit in a common source amplifier configuration is defined as the intrinsic gain of the MOS transistor, which can be expressed as

The detailed derivation process is omitted here. According to this formula, the intrinsic gain of the MOS transistor is inversely proportional to the overdrive voltage and the groove length modulation coefficient λ. Since λ is inversely proportional to the channel length L of the MOS tube, the intrinsic gain increases with the increase of L. Theoretically, the intrinsic gain of the MOS transistor can be increased by decreasing the overdrive voltage and increasing L. However, both of these operations slow down the working speed of the MOS tube. Therefore, in the actual circuit design, we need to make a trade-off between gain and speed. This balance between gain and speed has always been a central issue in the field of analog integrated circuit design. It is worth noting that the following equation can be seen

The intrinsic gain of the MOS transistor is similar to the intrinsic gain when designing the transconductance efficiency, but the intrinsic gain is additionally affected by the channel length. As the feature size of MOS devices continues to shrink, their intrinsic gain is decreasing, which poses an increasing challenge to our designs.

In addition, we need to be wary that too low an overdrive voltage may cause the MOS transistor to enter the subthreshold region, where the operating characteristics of the MOS transistor are very different from those in the saturation region, and many of the relevant formulas and theories will no longer apply.