FinFet Process Flow-Formation Of A Dumb Gate

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The formation of fins (Fin) and their importance

The fins are a key component of the three-dimensional structure of FinFET devices, which resembles the shape of a fish's fin, hence the name. The height of the fins directly determines the gate width of the FinFET, which is critical for controlling current flow. In the 22nm and below technology nodes, due to the very small fin size, it is usually achieved by patterning techniques such as SADP (Self-Aligned Double Patterning) or SAQP (Self-Aligned Quadruple Patterning).

Preliminary treatment with ILD layer deposition

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ILD layer deposition

Subsequently, a layer of ILD (Inter Layer Dielectric) is deposited on the cleaned wafer, which is generally SiO2 Coat. The primary role of ILD is to provide galvanic isolation between the fins and as a filler material in the subsequent CMP (Chemical Mechanical Polishing) process. Choosing the right ILD material is important to ensure good electrical properties and flatness.

ILD CMP

This is followed by ILD CMP, which uses silicon nitride (SiN) as the endpoint detection material for chemical mechanical polishing. The goal of the CMP is to make the surface of the ILD layer very flat to facilitate subsequent patterning and etching operations. The amount of polishing must be precisely controlled during the CMP process to avoid excessive erosion of the critical structures underneath.

Remove the SiN and Pad Oxide Layer

Once the CMP is complete, the silicon nitride hard mask covering the fins needs to be removed, as well as the pad oxide layer. This step is usually done by wet etching, which not only removes these temporary protective layers, but also exposes the silicon surface on top of the fin in preparation for subsequent doping.

Sacrificial oxide layer growth and well zone doping

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Sacrificial oxide growth

Immediately after, a thin layer of sacrificial oxide grows on the surface of the fin. This layer is used to protect the fins from direct damage during subsequent well doping. In addition, sacrificial oxide can help define the boundaries of the doping region and improve doping accuracy.

Doping in the well area

A well zone is applied to implant the mask, and ion implantation is performed to form an isolation trap between the channel and the substrate. This step is to create a p-type or n-type well region that provides appropriate background doping for PMOS and NMOS devices, respectively. After that, the sacrificial oxide layer is removed and the wafer is cleaned to ensure that no residue affects the subsequent process.

Formation of a dumb gate structure

Deposition of matte-gate oxide layer

In order to construct a temporary gate structure, a dumb gate oxide layer is deposited on the wafer. This oxide layer will serve as the basis for subsequent polysilicon deposition and planarization.

Polysilicon deposition and CMP

Then, a layer of polysilicon is deposited on the entire surface of the wafer and flattened by CMP. The polycrystalline silicon layer will act as a temporary gate material until the final high-k metal gate replaces it. During the CMP process, the polysilicon layer thickness is uniform to support the subsequent patterning steps.

Hard mask deposition

Next, a hard mask (HM) is deposited on top of the polysilicon layer to guide the subsequent gate patterning. Depending on the technology node, if the gate spacing is greater than 80 nm, a single 193 nm immersion lithography can be used to form a line-space pattern; For smaller gate pitches, multiplication techniques such as SADP or SAQP are required. The choice of hard mask and the deposition conditions are critical for the accuracy of subsequent patterning.

Gate patterning

A gate mask is applied to create a line-empty pattern in the photoresist. After hardmask etching, photoresist stripping, and cleaning, a cutting mask is applied and the hardmask line pattern is cut off by etching. Finally, the polysilicon is etched using the resulting hard mask pattern to create a designed dumb gate structure.