What is the real gate line width of major manufacturers of advanced processes?

When we talk about chip manufacturing, numbers such as "7nm" and "5nm" are always regarded as the yardstick of performance. But many people don't know that since the 14nm process, these nanologos are no longer the true width of the transistor gate, but more like a "technical code" between manufacturers. The four giants of TSMC, Intel, Samsung, and SMIC each hold different "scaling magic", so that the number of nanometers marked continues to decrease and the performance continues to jump. Today, we're going to unveil the true process from 14nm to 3nm.

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First understand: what does the process "nanonumber" represent?

In the era of 28nm and earlier, the number of nanometers in the chip process does correspond to the physical width of the transistor gate - the narrower the gate, the more accurate the current control, the faster the transistor switching speed, and the stronger the chip performance. But when the technology advances to the 14nm node, the gate width has been reduced to the physical limit: no matter how narrow the gate is, there will be severe leakage, resulting in a surge in chip power consumption.

In order to continue Moore's Law, the industry has quietly changed the "rules of the game": nanometers no longer represent the true gate width, but achieve node naming with "equivalent performance" through transistor structure innovation, lithography technology upgrades, circuit design optimization and other means. To put it simply, the essence of the current "7nm" is "a process with performance equivalent to the ideal 7nm gate width", rather than actually making a 7nm wide gate.

The technical route of the four giants: differentiated breakthroughs from 14nm to 3nm

TSMC: An "industry benchmark" for steady iteration

As a global foundry leader, TSMC's process evolution is known for its "stability", and each generation of nodes achieves equivalent scaling through precise technology combinations, firmly occupying a dominant position in the high-end market.

- 14nm node (mass production in 2015): This is the first mass production of TSMC's FinFET (FinFET (Fin Field Effect Transistor) technology, marking the entry into the era of stereo transistors. The real gate width is about 20-25nm, and the contact area between the gate and the channel is increased through the 3D fin structure, and the leakage rate is reduced by more than 60% compared with 28nm. Although independent transistor density data is not disclosed, based on the evolution characteristics of 16nm (28.2MTr/mm²), the density has increased by about 20%, making it the preferred process for high-end chips of Apple and Qualcomm.

- 7nm node (mass production in 2018): EUV (extreme ultraviolet lithography) technology is introduced for the first time, replacing traditional DUV (deep ultraviolet lithography) with a 13.5nm wavelength laser to reduce the number of lithography times and improve accuracy. The true gate width is about 18-20nm, and the transistor density reaches 96.5MTr/mm² (high-performance version), which is nearly 3 times higher than 14nm. This process supports classic chips such as Kirin 990 5G and Apple A12, allowing mobile phones to achieve desktop-level performance.

- 5nm node (mass production in 2020): Optimized fin spacing and channel design based on FinFET architecture, compressed true gate width to 15-18nm, and transistor density in the logic region reaches 127MTr/mm². Through the combination of "multiple exposure + EUV", a 15% performance improvement and a 30% reduction in power consumption are achieved without increasing the complexity of lithography, and Apple A14 and M1 chips all use this process.

- 3nm node (mass production in 2022): Adhering to the last major iteration of the FinFET architecture, the true gate width is about 12-15nm, and the standard transistor density reaches 273MTr/mm², which is 70% higher than 5nm. With increased fin height and optimized gate metal stacking, a 10-15% performance jump and a 25-30% power consumption reduction are achieved. It is worth noting that its high-density version has a density of 290MTr/mm² weighted with SRAM, which has become the core process of AI chips such as NVIDIA H100.

TSMC's equivalent logic: with EUV lithography as the core, through architecture fine-tuning and process optimization, it steadily improves density and energy efficiency while controlling costs, and each generation of nodes accurately matches market demand.

Samsung: Radical and innovative "tech gambler"

Samsung is one of the few practitioners of "architecture skipping" in the industry, and in order to catch up with TSMC, it boldly adopts new technologies at key nodes in exchange for a first-mover advantage at the expense of part of the yield.

- 14nm node (mass production in 2016): Same FinFET technology, but the initial yield is only about 50%. The true gate width is about 25-30nm, and the transistor density is 32.5MTr/mm², which is about 15% lower than TSMC's products in the same period. It has gradually stabilized through later optimization and has become an important choice for Android flagship chips, but the power consumption control is slightly inferior to the TSMC version.

- 7nm node (mass production in 2019): Initially, it tried to achieve the equivalent of 7nm with DUV multiple exposure, with a real gate width of about 18-22nm and a transistor density of 95.3MTr/mm², which is close to TSMC's level. However, the multiple lithography of DUV leads to complex processes, and the yield rate is less than 80% for a long time, and it is only later that it turns to EUV technology optimization to restore market trust.

- 5nm node (mass production in 2020): As an improved version of 7nm, the density is mainly improved by reducing the fin spacing, with a true gate width of about 15-18nm and a transistor density of 127MTr/mm². However, due to the lack of breakthrough in the architecture, the energy efficiency improvement is limited, and the density has no advantage over TSMC's same node, and it is only applied in some chips in the Android camp.

- 3nm node (first released in 2021): The world's first mass-produced GAAFET (surround gate transistor) process, replacing the fin structure of FinFETs with nanosheets, with a true gate width of about 12-15nm. By controlling the channel around the gate, the leakage rate is reduced by 50%, and the write voltage is only 0.23V. Its transistor density is 170MTr/mm², which is 38% lower than TSMC's 3nm, but the GAA architecture lays the foundation for subsequent nodes.

Samsung's equivalent logic: take transistor architecture innovation as a breakthrough, lay out next-generation technologies such as GAA in advance, use the strategy of "release first and then optimize" to seize the opportunity to name nodes, and sacrifice short-term yield in exchange for long-term technical discourse.

Intel: The "technology giant" who gets up early and catches up with the evening

As the hegemon of the x86 architecture, Intel once led the industry with its high-K metal gate technology in the 45nm era, but the slowness in EUV layout led to the backwardness of advanced processes, and it could only catch up through "node renaming" and architecture optimization.

- 14nm node (mass production in 2014): This is one of Intel's most successful nodes, using the FinFET architecture, with a true gate width of about 20-25nm and a transistor density of 43.5MTr/mm². Through multiple optimizations, 14nm++ and 14nm++ versions have been derived, and the performance has continued to improve, supporting the Core i7 and i9 series processors for up to 8 years, showing strong iterative capabilities.

- 7nm node (renamed Intel 7, mass production in 2022): The originally planned 7nm was changed to DUV optimization due to EUV delay, with a true gate width of about 15-18nm and a transistor density of 180MTr/mm². Intel has made it clear that its performance is benchmarked against TSMC's 5nm, achieving a 10% performance improvement and a 30% power consumption reduction through enhanced FinFET and circuit design optimization, mainly used in its own server chips.

- 5nm node (renamed Intel 4, mass production in 2023): Introducing EUV lithography technology for the first time, with a true gate width of about 12-15nm and a transistor density of 300MTr/mm². Using the early technology of high NA EUV, the line width is reduced while improving the lithography accuracy, and the performance is improved by 20% compared to Intel 7, finally achieving benchmarking with TSMC's 3nm.

- 3nm node (Intel 3, 2024 trial production): An optimized version based on Intel 4, with a true gate width of about 10-12nm and a transistor density of 520MTr/mm² through GAA architecture prototypes and lithography process upgrades. It is planned to be mass-produced in 2025, with the goal of catching up with TSMC's 2nm level in the field of high-performance computing, but it is still in the technical verification stage.

Intel's equivalent logic: Clarify the benchmarking relationship with the mainstream of the industry through "node renaming", use mature FinFET iteration and EUV supplementation, focus on the density and performance requirements of high-performance computing scenarios, and avoid the energy efficiency competition of mobile terminals.

SMIC: The "rising star" that broke through the blockade

Due to the limitations of external equipment, SMIC cannot obtain the most advanced EUV lithography machine, and can only achieve an "asymmetric breakthrough" in advanced processes through DUV multiple exposure technology, and every step is full of technical games.

- 14nm node (mass production in 2019): This is a sign that SMIC has entered the FinFET era, using DUV lithography to achieve a true gate width of about 25-30nm and a transistor density of about 35MTr/mm². Although the density is about 20% lower than that of the TSMC version, it has achieved independent mass production, broken the foreign monopoly, and provided a reliable choice for domestic chip design companies.

- 7nm node (N+1/N+2 process, pre-production in 2020): Equivalent 7nm performance is achieved through "DUV quadruple exposure" technology without EUV. The true gate width is about 20-22nm, and the transistor density reaches 90MTr/mm², which is 157% higher than 14nm. Although the lithography step has more than 100 layers, and it is extremely difficult to control yield and cost, it has successfully mass-produced chips such as Kirin 9000S, showing strong technical capabilities.

- 5nm/3nm node (N+3 process, under development): According to public information, SMIC is exploring the equivalent 5nm path through the combination of "DUV+Chiplet (chiplet)" - splicing chips made by multiple DUVs to achieve high-density integration. The 3nm node relies on GAA architecture research and development and domestic equipment breakthroughs, which is difficult to mass-produce in the short term, but has completed key technology verification.

SMIC's equivalence logic: under equipment limitations, DUV multiple exposure as the core, combined with advanced packaging technologies such as Chiplet, and the asymmetric route of "process innovation + packaging compensation" to achieve a leapfrog breakthrough in advanced processes.

Conclusion: The technological game and future behind nanonumbers

From 14nm to 3nm, the technical routes of the four major manufacturers clearly show the evolutionary logic of the industry: when the physical limit approaches, the continuation of Moore's Law no longer relies on a single line width reduction, but is the comprehensive result of architecture innovation, lithography upgrades, and packaging breakthroughs. TSMC's stability, Samsung's aggressiveness, Intel's catch-up, and SMIC's breakthrough, four different technology choices, have jointly written an innovation epic in the semiconductor industry.

Node	Company	Gate width reference value	Transistor density(MTr/mm²)
14nm	Intel	20~25nm	43.5
	TSMC	20~25nm	-
	SUMSUNG	25~30nm	32.5
	SMIC	25-30nm	35
7nm	Intel	15~18nm	180
	TSMC	18~20nm	96.5
	SUMSUNG	18~22nm	95.3
	SMIC	20-22nm	90
5nm	Intel	12~15nm	300
	TSMC	15~18nm	171.3
	SUMSUNG	15~18nm	127
	SMIC	-	-
3nm	Intel	10~12nm	520
	TSMC	12~15nm	273
	SUMSUNG	12~15nm	127

In terms of gate width, some processes do not disclose accurate values due to the confidentiality of manufacturers' technologies, and the reference values are mostly derived from the industry's measured and derived SRAM units. The data comes from the Internet, there may be certain deviations, for reference only.