Wafer Manufacture And Test

Wafer Manufacture and Test

Wafer manufacturing in semiconductor integrated circuit manufacturing can be divided into five manufacturing stages:

This document describes the first three steps as follows:

· Wafer Preparation

· Wafer Manufacture

· Wafer test

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Wafer preparation
In wafer Manufacture, the trend is to increase in size, which has the following implications: Productivity: Increasing wafer size can significantly improve productivity. When processing large wafers, the total number of chips that can be produced per unit of time increases due to the significant increase in the number of chips that can be accommodated on each wafer.
Production costs: Increasing wafer size can reduce production costs. Large wafer sizes reduce wafer-to-wafer dicing losses, further improving material utilization, while reducing the average cost per die.

Chip design: Large wafer sizes provide more space for chip design, enabling designers to achieve more complex and efficient circuit designs on a single wafer.
Process complexity: Increased wafer size also increases the complexity of the manufacturing process. For example, there are higher requirements for the uniformity of monocrystalline silicon growth, and parameters such as temperature and rotation speed need to be precisely controlled when drawing large-size monocrystalline silicon rods.

Equipment investment: The production line of large-size wafers requires special equipment, such as the cost of a single EUV lithography machine exceeds 100 million US dollars, and the supporting deposition and etching equipment is expensive.

Wafer Manufacture

Wafer manufacturing is the core link of semiconductor integrated circuit manufacturing, which is in accordance with a certain process flow, through repeated wafer cleaning, thin film preparation, photolithography patterning, etching and doping and other processing processes, and finally complete the chip manufacturing of integrated circuits on the wafer.
Wafer manufacture facilities are often divided into different zones based on individual process modules to ensure a smooth and efficient production process.

Lithography Zone: The designed circuit pattern is transferred to the surface of the wafer. Exposure, development, and etching are performed by photoresists and reticles. The photoresist undergoes a chemical reaction under UV light to form a pattern that corresponds to the pattern of the reticle. Then, the area that is not protected by the photoresist is removed by etching to form the desired circuit structure. As the feature size of the device decreases, the wavelength of the light source used by the lithography machine shifts to the deep ultraviolet direction to improve the lithography accuracy. Nowadays, the lithography room is mostly illuminated with yellow light, so the lithography room is sometimes called the yellow room area.
Etching Zone: Removes material from the surface of the wafer to form a specific pattern. This includes both wet etching and dry etching. Wet etching uses a chemical solution to remove material, while dry etching removes material by physical or chemical methods such as plasma or reactive ion beams. In the early days, it was mainly wet etching, which was usually cleaned in one area. However, as the feature size of the device decreases, anisotropic dry etching is used more. Dry etching provides better sidewall control and critical dimension control to meet the needs of finer circuit structures.

Ion implantation zone: Adjust the electrical properties of the wafer surface to form the desired doping layer. An accelerated beam of doped atoms is used to bombard the surface of the wafer using an ion implanter, injecting impurity atoms into the wafer. Injected wafers typically need to be annealed to repair the damage and activate the doped atoms. In the early days, semiconductor doping mainly adopted the high-temperature furnace diffusion process. However, with the decrease of the characteristic size of the device, the requirements for the morphology of PN junction depth and impurity concentration distribution in silicon are increased, and ion implantation technology has gradually become the mainstream doping method. Ion implantation technology has the advantages of high doping concentration, good uniformity and strong controllability.
Thin film area: Various thin films are formed on the surface of the wafer, such as an insulating layer, semiconductor layer, or conductor layer. These include methods such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). CVD deposits gaseous compounds on substrates through thermal decomposition or chemical reactions; PVD deposits the material onto the substrate through physical processes such as evaporation or sputtering. Thin film preparation is widely used in wafer fabrication. For example, SiO₂ films are often used as insulating layers, and polycrystalline silicon films are used to make transistor gates, etc.

Diffusion Zone: The name diffusion zone is still used, although the high-temperature furnace diffusion process is almost no longer used in modern wafer manufacturing. Today, this area is mainly used for processes such as thermally grown silica films, conventional thermal annealing, and rapid thermal annealing (RTA). As the feature size of the device decreases and the process requirements increase, the work in the diffusion region also changes. Now, this area is more focused on the quality of the silicon oxide film and the efficiency of the annealing process.
Metallization Zone: A metal interconnect layer is formed on the surface of the wafer to connect the individual devices together to form a complete circuit. Including the aluminum metallization process and the Damascus process of copper metallization, etc. The aluminum metallization process requires electron beam deposition of aluminum, magnetron sputtering aluminum, and dry etching of aluminum; The Damascus process of copper metallization, on the other hand, creates interconnecting layers by filling copper into pre-etched trenches. With the reduction of the feature size of the device and the improvement of process requirements, the Damascus process of copper metallization has gradually become the mainstream metallization method. This process can avoid the contamination of the underlying parts of the device by copper, and improve the performance and reliability of the circuit.

Epitaxial region: Growing a thin film of monocrystalline silicon on a silicon substrate (homogeneous epitaxy) or a thin film of other materials on a silicon substrate (heteroepitaxy) to meet the needs of a specific device. Methods such as vapor phase epitaxy (VPE) are included. A new layer of monocrystalline silicon or a thin film of other material is deposited on the surface of the wafer through a chemical reaction. The epitaxial process is widely used in the manufacture of high-performance integrated circuits and special devices. For example, epitaxial layers can be used to make high-speed transistors, low-power devices, and so on. In order to further improve the accuracy and efficiency of lithography, extreme ultraviolet lithography (EUVL) technology has emerged; In order to improve the performance and efficiency of the etching process, atomic layer etching (ALE) technology has emerged, among other things. The application of these new technologies makes the wafer manufacturing process more sophisticated, efficient and reliable.

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Wafer Test
Wafer test is a critical part of the semiconductor manufacturing process, designed to ensure that each chip meets design specifications and functional requirements prior to packaging. Wafer testing includes a variety of in-line inspections and measurements during the wafer fabrication process, as well as functional and performance testing of integrated circuit chips with a probe card after chip fabrication. The following is a detailed description of the wafer testing phase:

In-line inspection and measurement purpose: to conduct real-time inspection during the wafer manufacturing process to ensure that the process parameters meet the standards, and to detect and correct process deviations in time. At the same time, various physical parameters of the wafer are accurately measured, such as diameter, flatness, thickness, etc., to ensure that the quality of the wafer meets the standard requirements.

Method: Optical or other alignment techniques were used to precisely align the test points on the wafer with the probe card for real-time inspection. At the same time, advanced measuring instruments and equipment, such as laser interferometers, atomic force microscopes, etc., are used to perform non-contact measurement of wafers.

Application: In-line inspection is widely used in various process modules in the wafer manufacturing process, such as lithography, etching, doping, etc., to ensure process quality and production efficiency. Measurements are used to ensure that the quality of the wafer meets the standard requirements and to provide data support for process optimization. The purpose of probe card testing is to test the electrical performance of each chip on the wafer, and screen out qualified chips for subsequent packaging. Method: A probe card was used to probe the electrical contact points of each bare die for functional testing. The probe on the probe card is in direct contact with the solder joints or protrusions on the chip, and the chip signal is derived, and then the automatic measurement is realized with relevant test instruments and software control. Technical details: Probe cards are a key tool for wafer functional verification testing, typically consisting of probes, electronic components, wires, and printed circuit boards (PCBs). The probe on the probe card is as thin as a hair and is able to make precise contact with the pad on the die. Technology Evolution: As device feature sizes decrease and process requirements increase, probe card testing techniques continue to evolve. For example, flying probe testing technology has emerged, which enables direct contact with probe card connector pins for complete continuity testing between PCBs and ceramic plates, eliminating the need for application-specific interface boards or fixtures. The purpose of the faulty chip marking method: after the defective chip is detected, it is marked as unqualified so that it can be eliminated in the subsequent wafer dicing and packaging process.

Method: In the early stage, the faulty chip was inked so that it could be rejected for packaging. The computer that is now multi-purpose testing will record the location of the faulty chip on the wafer bitmap. Technology evolution: With the development of automation and information technology, the method of marking faulty chips is also constantly improving. Now, computer-recorded wafer bitmaps can more accurately locate faulty chips, improving productivity and product quality. The Impact of the Evolution of Test Methods on Production Efficiency and Product Quality: Productivity: Automated Testing, With the development of automated testing technology, the wafer testing process has become more efficient and reliable. Automated testing can reduce manual intervention and improve testing speed and accuracy, thereby increasing productivity; Intelligent testing, with the development of artificial intelligence technology, began to explore how to use machine learning algorithms to improve the testing process. For example, AI is used to identify changes in UI elements and automatically adjust test scripts. Or use machine learning models to predict which parts of your code are more likely to contain defects. Intelligent testing can further improve testing efficiency and accuracy, and reduce testing costs. Product quality: Early defect detection, through technologies such as online inspection and probe card testing, defective chips can be found early in the wafer manufacturing process, avoiding them from entering the subsequent packaging and testing process, thereby improving product quality; Accurate fault location, with the improvement of the fault chip marking method, the fault chip can be located more accurately, avoid misjudgment and missed judgment, and further improve product quality. These technologies and methods in the wafer test phase not only ensure the quality and performance of the chips, but also bring significant economic benefits to the semiconductor manufacturing industry by increasing production efficiency and reducing test costs.