TSMC's Advanced Process History: Technology Evolution and Device Innovation from N7 to N5, N3 to N2 (GAA process flow)

As a global leader in semiconductor technology and a leading enterprise in the wafer foundry industry, TSMC has taken the lead in pioneering a professional integrated circuit manufacturing service business model since its establishment in 1987, supporting technological breakthroughs and innovation in the global semiconductor industry ecosystem by continuously promoting advanced process evolution and device structure innovation. Its advanced process evolution from 7nm (N7) to 2nm (N2) is not only the epitome of the semiconductor technology revolution, but also profoundly affects the development pattern of downstream industries, constituting a series of key milestones in the logical chain of "technological breakthrough-performance leap-application expansion".

From the perspective of the technological evolution timeline, TSMC's advanced process nodes present a clear iterative path:

In 2018, the mass production of the N7 FinFET process was launched, marking the mature application of FinFET structure in advanced processes.

In 2020, the mass production of the N5 FinFET process was promoted to achieve the full integration of all-polar ultraviolet lithography (EUV) technology.

In 2022, the mass production of the N3 FinFET process will be realized, pushing the performance potential of FinFET device structures to the peak;

In 2025, it plans to mass-produce the N2 process, introducing full-surround gate (GAA) nanosheet technology for the first time, completing the device architecture leap from FinFET to GAA, forming a "planar to three-dimensional" technological revolution.

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In this process, each generation of processes continuously improves the performance, power consumption, and area (PPA) indicators of chips through device structure innovation and process optimization.

The N7 family opens the EUV era to improve lithography accuracy;

N5 further reduces feature size through full EUV process;

N3 is the final product of FinFET technology, achieving a significant breakthrough in energy efficiency ratio.

N2's GAA technology solves the physical limit problem of FinFET through a three-dimensional gate structure.

At the level of industrial impact, TSMC's advanced technologies provide core computing power support for downstream applications:

The N7 process supports the performance leap of smartphone chips and promotes mobile devices into the 5G era;

The high integration and energy efficiency ratio of the N5 process have become the key cornerstones of AI chips and data center processors, accelerating the commercialization of artificial intelligence and high-performance computing (HPC).

The N3 process further meets the needs of edge computing and intelligent terminals for low power consumption and high computing power.

The GAA technology of the N2 process will provide stronger computing power reserves for cutting-edge fields such as next-generation AI large models and quantum computing simulations.

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Through the deep coupling of technological innovation and industrial demand, TSMC's advanced processes not only define the technical standards of the semiconductor industry, but also become an important driving force for the development of the global digital economy. This chapter will use this technology evolution context as a framework to explain in detail the technological breakthroughs, device innovations and their far-reaching impact on the global semiconductor industry at each process node.

N7 family (7nm): the starting point of the EUV era

N7 (1st generation 7nm FinFET)

As TSMC's first 7nm FinFET process, N7 is a key node in the maturity of its FinFET technology, taking the lead in launching large-scale mass production in 2018 and becoming one of TSMC's fastest mass production technologies, providing an optimized manufacturing process for mobile computing and high-performance computing (HPC) components. In terms of performance, N7 has achieved a significant breakthrough compared to the previous generation process: compared with the 16nm process (N16), its speed is increased by about 30%, power consumption is reduced by about 55%, and logic density is increased by 3 times; Compared with the 10nm FinFET process technology, the logic gate density is increased by 1.6 times, the speed is increased by about 20%, and the power consumption is reduced by about 40%.

Compare metrics	Contrast processes	Improvement margin
Speed boost	N16	Approximate 30%
Reduced power consumption	N16	Approximate 55%
Increased logic density	N16	3times
The logic gate density is improved	N10	1.6times
Speed increases	N10	Approximate 20%
Reduced power consumption	N10	Approximate 40%

The FinFET 3D structure is the core foundation for N7 performance improvement, which effectively improves gate control ability and suppresses the short channel effect by optimizing the gate-channel contact design, thereby enhancing the electrical performance of the device. It can be intuitively observed that its fin structure further optimizes charge control efficiency through a finer three-dimensional layout, providing device-level support for the improvement of logic density and energy efficiency.

In terms of application and market performance, N7 is widely used in smartphones, HPC, and consumer electronics due to its excellent performance. In the second year of mass production (2019), customers have launched more than 110 new generation products based on the N7 process, demonstrating strong customer ecological advantages.

N7+ (Enhanced 7nm, EUV Debut)

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The N7+ (enhanced 7nm) process was mass-produced in 2019 and is the world's first commercial extreme ultraviolet (EUV) lithography foundry technology. The core breakthrough of this process lies in the introduction of EUV lithography technology, which uses 13.5nm extreme ultraviolet light as the light source, which significantly shortens the exposure wavelength compared to the 193nm wavelength of traditional deep ultraviolet (DUV) lithography technology, thus breaking through the physical limits of traditional optical lithography. The shorter wavelength enables EUV to directly enable higher resolution circuit pattern definition, reducing the reliance on complex multiple exposure techniques, which is key to streamlining the process.

The application of EUV technology has brought many practical benefits to N7+. By shortening the exposure wavelength, N7+ effectively reduces the number of mask layers and process complexity, thereby improving wafer production yield and overall productivity. These improvements not only optimize the performance and cost structure of the 7nm family, but also provide valuable experience for the development of more advanced process nodes in the future. As the first large-scale mass production application of TSMC's EUV technology, N7+ is regarded as an important "technical verification node", and its successful operation verifies the reliability and economy of EUV lithography in the mass production environment, laying a solid technical foundation for the subsequent N6, N5 and even N3 nodes to fully switch to full EUV processes. This strategic layout allows TSMC to take the lead in mastering the large-scale application capabilities of next-generation lithography technology in the competition for advanced processes, consolidating its technological leadership.

N6 (6nm, 7nm family optimization)

As an optimized version of TSMC's 7nm family, N6 is positioned as a "transition node with cost-benefit balance", and its core strategy is to achieve a balance between performance improvement and cost control through technical optimization and design compatibility. The process was officially mass-produced in 2020 and is based on the mature N7 technology platform, which is widely used in mid-to-high-end mobile devices, artificial intelligence (AI), network communications, digital consumer electronics (DCE) and other product fields, and also supports high-performance computing (HPC) scenarios. In terms of reducing customer migration costs, N6 adopts N7-compatible design rules and supports IP (intellectual property rights) reuse, which significantly reduces the design complexity and development investment when customers migrate from N7 to N6. Customers can directly leverage IP modules from the mature N7 ecosystem without redeveloping or making large-scale adjustments to existing designs, reducing time-to-market and R&D risk.

In terms of PPA (power/performance/area) performance, N6 is significantly optimized compared to N7. In terms of logic density, N6 has an 18% increase in logic density compared to N7, which directly improves the area efficiency of the chip, helping to reduce chip size or integrate more functional units in the same area. In addition, through the further application of EUV lithography technology and the optimization of process complexity, N6 has also made progress in improving yield and shortening production cycles, indirectly reducing the manufacturing cost per chip. In response to power optimization needs, TSMC has also developed N6e™ ultra-low power (ULP) technology, and its process design kit (PDK) is ready in 2023, providing more flexible options for power-sensitive application scenarios.

The launch of N6 is a key part of TSMC's "family" process strategy, aiming to meet the needs of different customers through differentiated technology paths. For high-end customers who pursue ultimate performance, the N7 series (such as N7P, N7+) provides stronger performance support; For the cost-sensitive midmarket, the N6 is ideal for balancing performance and cost thanks to its compatibility with the N7, optimized logic density, and controllable cost. This family layout allows TSMC to cover a wide range of application scenarios from high-end to mid-range, enhancing its market competitiveness in the field of advanced logic processes.

N5 family (5nm): the pinnacle of full EUV and FinFET

N5 (1st generation 5nm FinFET)

As TSMC's first-generation 5nm FinFET process, N5 is regarded as the pinnacle of performance of the FinFET architecture, and its technological breakthroughs and market applications have jointly established this position. The process, which started large-scale mass production in 2020, is TSMC's second-generation extreme ultraviolet (EUV) lithography node, which has achieved significant optimization in terms of power consumption, performance and area (PPA), and is widely used in high-performance products such as Apple's A14/A15/M1 series chips, AMD Zen4 CPUs, and some models of NVIDIA Hopper GPUs.

The technical advantages of N5 are first reflected in the mature application of full EUV lithography technology. As a second-generation EUV process, N5 fully adopts EUV technology, which effectively reduces process complexity and achieves finer pattern transfer accuracy by optimizing mask layer design and process flow, providing key support for transistor density improvement and device performance optimization. This technical feature enables innovative scaling capabilities for density enhancement of logic, static random access memory (SRAM), and analog circuitry, especially for mobile devices and high-performance computing (HPC) scenarios.

In terms of performance, N5 shows a significant improvement compared to the previous generation N7 process, providing about 20% faster speed or about 40% lower power consumption, which makes it the core manufacturing process in mobile terminals and data centers. Through the in-depth optimization of the FinFET device structure and the efficient integration of EUV technology, the N5 maximizes the performance potential of the FinFET architecture while maintaining the stability of the architecture, marking that TSMC has reached the peak level of FinFET scaling technology.

N4/N4P (4nm & Enhanced)

The N4/N4P process technology is a continuous iterative product of TSMC's 5nm family, reflecting its business logic of extending the process life cycle through a "half-node" strategy. TSMC has not made disruptive innovations in 5nm technology, but has continued to improve process performance and density while controlling R&D costs while controlling R&D costs to meet customers' needs for iterative upgrades, thereby consolidating market competitiveness.

As an enhanced version of the N5, mass production began in 2022, with the core goal of achieving a small increase in performance and density over the N5. This process has been applied to mobile chips such as Apple A16 and Snapdragon 8 Gen 2, and through fine optimization, it provides better energy efficiency performance for mobile devices while maintaining compatibility with N5 design rules. This design compatibility significantly reduces customer migration costs, allowing chip design companies to quickly iterate products based on the mature 5nm ecosystem, further strengthening the attractiveness of TSMC's process platform.

In order to further expand the application scenarios of the 5nm family, TSMC has launched derivative versions such as N4P and N4X. Among them, N4P is positioned as a performance-optimized version, which entered the risk production stage in July 2022, with an 11% performance improvement compared to the N5, and has been adopted by high-end mobile chips such as Snapdragon 8 Gen 3. N4X, on the other hand, is optimized for high-frequency and high-performance scenarios, which can meet the requirements of high-performance computing (HPC) fields such as data centers.

Through the differentiated positioning of N4, N4P and N4X, TSMC has achieved accurate coverage of mobile and data center market demand. N4 meets the needs of mainstream mobile devices with balanced energy efficiency and density, N4P serves high-end mobile terminals through performance enhancement, and N4X focuses on high-frequency scenarios to support the computing power needs of data centers. This multi-version collaboration strategy not only extends the technical life cycle of the 5nm process, but also consolidates TSMC's leading position in the field of advanced processes through deep penetration of market segments.

N3 family (3nm): the final work of FinFET

N3/N3E (1st generation 3nm and enhanced)

As the final work of FinFET technology, TSMC's N3 family also lays the process foundation for the subsequent transformation of GAA (Full Surround Gate) technology. N3 (the first generation of 3nm process) will start mass production in 2022 and is the last generation of high-end process nodes of the FinFET architecture, marking TSMC's breakthrough in the physical limit of the FinFET technology route. Compared with the previous generation N5 process, N3 achieves about 70% improvement in logic density, while performing significantly in terms of energy efficiency and performance: 10-15% faster at the same power consumption and 25-30% lower at the same speed, demonstrating the ultimate optimization of the FinFET architecture at the 3nm node.

In order to further optimize yield, cost, and scope of application, TSMC launched N3E (enhanced version of the 3nm process) in 2023 and entered mass production in the fourth quarter of the same year. As the industry's first optimized 3nm technology node, N3E further improves the overall performance on the basis of N3, achieving up to 20% speed improvement, more than 30% power consumption savings, and about 1.6 times more logic density than the N5 process. Its optimized process characteristics make it more widely applicable and can meet the needs of high-performance computing (HPC), mobile devices and other fields, such as MediaTek's Dimensity flagship chips and NVIDIA's next-generation GPUs.

The technological evolution of the N3 family also includes continuous iterations of subsequent versions. The N3P (Performance Optimized Edition) will be mass-produced in 2024, and through process optimization such as optical reduction, it further improves performance, reduces power consumption, and increases transistor density while maintaining compatibility with N3E design rules. Driven by strong demand in the HPC and mobile device markets, TSMC's 3nm process production capacity in 2024 will triple compared to 2023, but it is still in short supply, reflecting the competitiveness of the N3 series process in the high-end chip market.

As the final node of FinFET technology, the N3 series has accumulated key technical experience through extreme process scaling, laying the foundation for the subsequent transformation of GAA architecture. Although detailed data on specific fin width and gate length are not disclosed, the significant increase in logic density (such as N3E is about 1.6 times higher than N5) confirms TSMC's ultimate exploration of 3D device stacking and material engineering under the FinFET structure, and these process experiences directly support the R&D and mass production preparation of next-generation GAA technology.

N3X (Extreme Performance Edition)

As a "special optimization node" in TSMC's 3nm technology family, N3X's core technical logic lies in in-depth customization for the high-frequency requirements of high-performance computing (HPC) scenarios. TSMC is expanding the 3nm technology family to meet diverse customer needs, and N3X is a process node built for HPC applications under this strategy, aiming to provide higher clock speed support for ultra-high-performance scenarios such as high-performance CPUs, desktops, and data center GPUs.

In terms of specific performance optimization, N3X balances performance and power consumption through refined voltage regulation strategies. Compared with the N3P node, when the operating voltage (Vdd) is reduced from 1.0V to 0.9V, N3X can reduce power consumption by 7% at the same frequency or increase computing performance by 5% at the same chip area. At the same frequency, the transistor density is about 10% higher than that of N3P. At the same time, to meet the performance requirements of extreme load scenarios, the N3X supports an operating voltage of up to 1.2V, which allows it to steadily increase the clock frequency under high load conditions, further unleashing the computing potential of the processor.

Performance metrics	Comparison conditions	N3X Improvements	Voltage conditions
power consumption	same frequency	Lower 7%	1.0V→0.9V
Computing performance	Same chip area	Increase 5%	1.0V→0.9V
Transistor density	same frequency	Increase 10%	-

The technical positioning of N3X fully reflects TSMC's capabilities in the field of process customization. Through special optimization for HPC scenarios, TSMC can provide differentiated solutions for different application needs under a unified technical architecture, which not only meets the stringent requirements of mobile devices for energy efficiency, but also realizes deep adaptation to ultra-high-performance computing scenarios through nodes such as N3X, further consolidating its technical flexibility and market competitiveness in the field of advanced processes.

N2 family (2nm): the beginning of the GAA era

N2 (1st generation 2nm GAA nanosheets)

As TSMC's first process node to adopt full surround gate (GAA) nanochip transistor technology, N2 marks the semiconductor industry's official entry into the "post-FinFET era", and its technological innovation is reflected in the all-round breakthrough of device structure and performance. The process is expected to start mass production at the Baoshan plant in Hsinchu, Taiwan in the second half of 2025, becoming one of the world's first commercialized 2nm GAA technologies.

From the perspective of device structure, GAA nanosheet transistors have achieved a fundamental upgrade compared with traditional FinFETs. By adopting a 360-degree full-surround gate design, the N2 transistor significantly enhances the electrostatic control ability of the conductive channel, effectively reducing the leakage current, which is the core foundation of its power consumption optimization. At the same time, the tunability of nanosheet width allows the process to achieve a dynamic balance between performance and power consumption: wider nanosheets can increase the drive current for enhanced performance, while narrower nanosheets can reduce power consumption to meet the needs of different application scenarios. In addition, the stacked nanosheet structure greatly improves the transistor density, with a 15% increase in transistor density for N2 compared to the N3E process, and the size of the HD SRAM cell is reduced to 0.0175 μm² (corresponding to SRAM density of 38 Mb/mm²), effectively solving the industry problem of SRAM scaling stagnation in recent years.

In terms of performance and power consumption, N2 shows significant advantages: with the same number of transistors and frequency, the power consumption is reduced by 25%-30% compared to N3E; With the same number of transistors and power consumption, the performance is improved by 10%-15%. These improvements are due to the electrostatic advantages of GAA structures and process optimizations, such as the integration of ultra-high-performance metal-insulator-metal (SHP MIM) capacitors, which have a capacitance density of up to two times that of previous ultra-high-density metal-insulator-metal (SHD MIM) designs, while reducing chip resistance (Rs) and via resistance (Rc) by 50%, further enhancing power stability.

Technological maturity is a key support for the commercialization of N2. Pre-production data show that the defect density (d0) of N2 is lower than that of N3, N5 and N7 nodes in the same development stage, and the defect density decreases faster than that of previous FinFET nodes (such as N3/N3P and N5/N4). The high yield verification further confirms its stability: the 256 Mb SRAM module has an average yield of over 90% and an HD SRAM density of 38 Mb/mm², making it suitable for high-end applications such as smartphones and high-performance computing (HPC).

Compared with the nanowire structure used in Samsung's 3nm GAA process, TSMC's N2 nanosheet design has more advantages in terms of commercialization maturity. The nanosheet structure boosts the drive current through a wider conductive channel and has a higher stacking density, allowing more transistors to be integrated in the same chip area. Although nanowires have better static control in theory, there are challenges in manufacturing complexity and performance scalability. N2's technology selection not only balances performance and process feasibility, but also ensures commercialization capabilities by verifying customer needs (such as chiplet design integration) and large-scale tape-out testing in advance, and its initial customer demand has exceeded expectations.

On the whole, N2 has achieved a double breakthrough in device physics and manufacturing process through the GAA nanosheet structure, and its synergistic effect of performance improvement, power consumption optimization and density growth not only consolidates TSMC's leading position in the field of advanced processes, but also promotes the entire semiconductor industry to take a key step towards the technological revolution of the "post-FinFET era".

N2P/A16 (Enhanced vs. 1.6nm transition)

The N2P/A16 process node represents the continuous evolution of TSMC's GAA (Full Surround Gate) technology and is a key stage in the transition of its advanced process from 2nm to 1.6nm. As an extension of the N2 series, N2P is positioned as a 2nm enhanced version and is scheduled to achieve mass production in 2026, which can reduce power consumption by 5%-10% or improve performance by 5%-10% compared to N2 under the same voltage and design conditions through further optimization of GAA device structure and process. The core innovation of the A16 (1.6nm) process is the core of this stage of technological breakthrough, and its core innovation lies in the introduction of superrail (SPR, backside power supply technology), which effectively frees up the front-side wiring space by moving the traditional power supply network located on the front of the wafer to the back, significantly reducing the problem of metal wire congestion, and creating conditions for improving logic density and signal routing efficiency.

In terms of technical performance, A16 shows comprehensive advantages over N2P: 8%-10% performance improvement under the same voltage and design conditions, 15%-20% reduction in power consumption at the same frequency and number of transistors, and 7%-10% increase in logic density. This enhancement makes it particularly suitable for high-performance computing (HPC) applications with complex signal routing and power supply network intensive chip design needs, such as AI-accelerated chips and high-end server processors.

From the perspective of technological evolution, the emergence of N2P/A16 is the inevitable result of TSMC's technical route from N7 to 1.6nm, which can be sorted out into four key stages:

EUV popularization (extreme ultraviolet lithography technology was introduced for the first time in the N7 stage to lay the foundation for high-precision processes)

FinFET optimization (continuous improvement of fin FET structure from N5 to N3E stage to achieve a balance between performance and power consumption)

GAA transformation (full-surround gate devices were officially adopted in the N2 stage, breaking through the physical limits of FinFET) Backside power supply (the A16 stage reconstructed the power supply network through superrail technology to free up front-side wiring space)

This route reflects the technological transition logic from "process miniaturization" to "structural innovation + system optimization".

The launch of the N2P/A16 process will have a significant impact on the energy efficiency ratio of AI chips after 2026. AI chips have extremely high requirements for logic density, signal processing power and power supply efficiency, and the front wiring space released by the A16 through the back power supply technology can alleviate the metal wire congestion problem of complex AI computing units, the 7%-10% logic density increase can support more computing core integration, and the 15%-20% power consumption reduction directly improves the chip energy efficiency ratio. Especially for large model training chips in HPC scenarios, the energy efficiency advantages of A16 at the same frequency and number of transistors will help achieve a balance between higher computing power density and lower power consumption, and promote further breakthroughs in AI computing capabilities.

Summary of technological evolution: core breakthroughs from FinFET to GAA

The continuation and innovation of Moore's Law are the core threads of TSMC's advanced process evolution. Comparing the technology iteration of the N7 to N2 nodes horizontally, its PPA (performance, power consumption, area) improvement curve shows a trend of continuous optimization: the N7+ node introduces EUV lithography technology for the first time, the N5 node achieves full EUV application, the N3 node completes the ultimate optimization of the FinFET architecture, and the N2 node further promotes the synergistic improvement of performance, power consumption and area through the first mass production of GAA nanosheet technology.

Longitudinal analysis of the innovative evolution of device structures, from FinFET to GAA, is the key to pushing the physical limits. In the FinFET era, the main way to increase transistor density is to reduce the number of fins per transistor (depopulation), rather than simply reducing the feature size. At the same time, the driving current and gate electrostatic control ability per unit area are improved by reducing the fin spacing, increasing the fin height and optimizing the vertical fin sidewall profile. However, the FinFET architecture faces the bottleneck of the decrease of carrier mobility after the fin thickness is too small, so SiGe material is introduced at the N5 node to improve the hole mobility. GAA technology realizes a full-by-circumference gate design through horizontal nanosheet structure (alternating Si and SiGe layers), which enhances the electrostatic control of the gate to the channel from all sides, significantly increases the gate-channel interface area, and solves the scaling limitation of FinFET. This structure allows for a universal single-fin transistor design (currently FinFETs average two fins per transistor), which is a natural evolution to improve the power performance of each fin while enabling an effective reduction in SRAM cell size (up to 0.0175 μm² for the N2 node HD SRAM cell size).

Combined with the working voltage comparison curves of Planar→FinFET→ GAA, it can be seen that GAA shows significant advantages under low voltage conditions. Its full-surround gate structure can maintain good current driving capability at lower operating voltages, thereby effectively reducing power consumption, which is directly related to the improvement of power performance by GAA.

TSMC continues Moore's Law through collaborative innovation of "material-structure-process": the introduction of heterogeneous materials such as SiGe at the material level improves carrier mobility; At the structural level, it has evolved from FinFET of 3D fins to GAA of full-surround nanosheets, breaking through the density bottleneck of reducing the number of fins. At the process level, the realization of structural innovation is supported by the large-scale application of EUV lithography technology, the integration of backside power supply technology, and advanced manufacturing processes such as sacrificial materials (such as selective epitaxy and highly selective etching required by GAA). Although GAA is more complex to manufacture, it represents the next stage in semiconductor manufacturing, laying the foundation for subsequent technologies such as CFET to further improve transistor density.

Analysis of device structure innovation: from three-dimensional to full-surround

The evolution of transistor structures has gone through the development path from planar to fin field-effect transistors (FinFETs), to full-surround gate transistors (GAAFETs) and subsequent multi-bridge channel field-effect transistors (MBCFETs). The core driving force of this evolution is to address the challenge of short channel effect caused by the continuous reduction of device size at advanced process nodes by optimizing gate control capabilities.

As a typical representative of three-dimensional fin structure, FinFET realizes three-sided control of the gate to the channel through vertical fins, which significantly optimizes the subthreshold leakage current and improves performance and density compared with planar transistors. However, the critical dimensions of FinFETs are dependent on the etching process, and when the fin thickness decreases, the carrier mobility decreases, requiring strain engineering (e.g., the introduction of SiGe materials) to improve mobility.

GAA nanosheet technology has realized the transformation from "three-dimensional fin" to "full surround gate", which adopts a horizontal nanosheet structure, etched the edge of the SiGe layer and deposited isolation oxides by growing alternating Si and SiGe superlattice layers on the wafer substrate, and then supporting the Si nanosheet through source-leakage epitaxial growth, and finally selectively removing the SiGe layer to expose the Si channel, combined with atomic layer deposition (ALD) to form a gate oxide layer, so that the gate can achieve four-sided control of the channel. Unlike the vertical fin structure of FinFET, the critical dimensions of GAA are defined by selective deposition and etching, and its 3D characteristics place higher demands on fabrication processes (e.g., atomic layer deposition, selective epitaxy, highly selective etching) and metrology.

From the physical point of view, GAA further enhances the electrostatic control ability of the channel by increasing the gate control area, effectively reduces the short channel effect, and improves the subthreshold slope. Under the same gate length conditions, GAA structures can control channel current more effectively than FinFETs, reduce leakage current, and support smaller transistor sizes without sacrificing performance or power. TSMC introduced nanosheet (GAA) structure for the first time in the 2nm (N2) process node, realizing the architectural change from FinFET to GAA, and its defect density decline trajectory is consistent with that of the previous generation of FinFET nodes, indicating that TSMC has successfully migrated its process learning and defect management experience to the GAA era, verifying the advantages of GAA technology in terms of power consumption, performance and density.

Characteristic	FinFET	GAA (Nanosheets)
Structure	Vertical fins	Horizontal nanosheets
Gate control method	Three-sided control	Full surround control on all sides
Key processes	Etching process (defining fins), strain engineering (e.g. SiGe boosting mobility)	Selective deposition and etching (defining nanosheets), atomic layer deposition (ALD) to form gate oxide layers
Advantage	Optimize subthreshold leakage current for improved performance and density	Better electrostatic control, reduced short channel effect, and support for smaller sizes
Challenge	The decrease of fin thickness reduces the mobility of carriers. Critical dimensions rely on etching	The manufacturing process is complex (atomic layer deposition, selective epitaxy, highly selective etching) and the measurement requirements are high

The maturity of GAA technology has laid a key foundation for future process nodes of 1nm and below. As an important architectural innovation after FinFET, GAA solves the limitation that FinFET is difficult to further improve performance after the number of fins is reduced through better gate-channel interface design and stronger scaling capabilities, and has become the core device structure that supports the continuous miniaturization of semiconductor processes.

Summary: The technical logic and industrial impact of TSMC's process evolution

The core logic of TSMC's continuous leadership in the field of advanced processes lies in building competitive barriers through the two-wheel drive of "technology leadership + ecological synergy". At the level of technological leadership, TSMC takes device structure innovation and process technology iteration as the core starting point: from the first introduction of EUV lithography technology at the N7 node, to the full EUV process coverage at the N5 node, and then to the N3 node as the final work of the FinFET architecture, until the N2 node fully shifts to the GAA (Gate-All-Around) architecture, forming a systematic structural evolution from FinFET to GAA. In this process, through strain engineering, backside power supply and other process optimization methods, TSMC continues to improve chip performance, reduce power consumption and increase integration density (PPA), effectively breaking through the physical limitations faced by traditional transistor scaling, such as solving the bottleneck of SRAM cell scaling stagnation.

At the level of ecological collaboration, TSMC significantly reduces customer migration costs by complying with design rules, building a complete IP ecosystem and end-to-end technical support. It simultaneously develops IP, advanced packaging (such as CoWoS, InFO, SoIC) and test technology, forming a full-process solution from chip design to manufacturing, and deeply collaborates with core customers such as Intel, NVIDIA, and AMD to promote the positive cycle of "process-design-product". This ecological barrier not only consolidates customer stickiness, but also accelerates the industrialization of new technologies.

TSMC's process evolution has had a profound impact on the global semiconductor industry. At the technical level, the layout of N2 and subsequent N2P, A16 and other process nodes will further consolidate its leading position in the field of logic device manufacturing, and the successful introduction of GAA architecture has laid the foundation for more advanced processes such as 1.6nm. At the industrial application level, through the capacity expansion of the Arizona factory (N4, N3/N2) and the Japanese factory (6/7nm), TSMC can effectively cope with the strong demand growth in the AI and HPC fields, and provide underlying manufacturing support for the global computing power competition. At the same time, the continuous optimization of PPA promotes the development of the semiconductor industry in the direction of higher energy efficiency ratio, and in diversified markets such as smartphones, automotive electronics, and the Internet of Things, TSMC's process has become the core engine driving terminal product innovation, helping to achieve green computing and sustainable development goals.