The Jargon that Newcomers New to Fab Need to Know

This is the basic vocabulary that you will hear and use every day in the fab, and must be understood no matter what department you are in.

Fab

Explanation: Fabrication Plant is the abbreviation of our entire manufacturing plant.

Key points: Different fabs have different codenames (e.g. Fab A, Fab B) and technical nodes.

2. Cleanroom

Explanation: The core area where we conduct chip manufacturing. The air is efficiently filtered and has extremely tight control of dust particles.

Bottom line: Why wear a Bunny Suit? Because the human body is the biggest source of pollution. A tiny particle of dust in the air that falls on a critical area of the wafer can lead to the entire chip being scrapped. There are grades of clean rooms, such as Class 1 and Class 10, and the smaller the number, the cleaner.

Lot

Explanation: The basic unit of production, usually a box (A Cassette/FOUP) wafer, the standard quantity is 25 pieces. All production instructions and data tracking are in lots.

Takeaway: You'll hear "Where did this Lot go?" all day long. ", "Check the data of that lot". The Lot ID is its ID number.

Wafer

Explanation: The substrate on which chips are made is usually high-purity silicon wafers. All our process steps are carried out on this circular "canvas".

Point: The mainstream sizes are 8" (200mm) and 12" (300mm). The larger the size, the more dies can be fabricated on a single wafer, and the more cost-effective it is.

Yield

Explanation: There is no one that the company is most concerned about. It refers to the percentage of good dies that pass all tests on a wafer to the total number of chips.

Key points: The yield rate directly determines the company's profitability. The work of all our engineers, whether process development, equipment maintenance or process optimization, is ultimately aimed at improving and stabilizing yields.

SPC (Statistical Process Control )

Explanation: A set of tools to monitor the stability of the production process, the most common is the control chart(Control Chart).

Key points: When you see the SPC chart of a certain parameter "red" or "alarm", it means that this process step may be out of control (OOC) and needs to be dealt with immediately, otherwise it will affect the yield of the entire lot. This is the "dashboard" of our engineers.

Category II：Core Process Flow

These terms describe the macro blueprint for chip manufacturing.

1. FEOL (Front-End-Of-Line)

Explanation: Refers to the process of manufacturing basic components (mainly transistors) on a wafer. All processes starting from the bare silicon wafer to the first metal layer (M1).

Key points: This is the "foundation and main structure" of the chip, which determines the core electrical performance of the chip. It includes isolation, gate, source-drain and other structures.

2. BEOL (Back-End-Of-Line)

Explanation: The process of fabricating multilayer metal interconnects on top of FEOL-completed transistors.

Key points: It's like laying complex wires, plumbing, and networking systems for a built building. These connections are responsible for connecting hundreds of millions of transistors to form a complete circuit.

3. Process Flow / Route

Explanation: A complete "recipe" for making a specific product with hundreds or thousands of detailed process steps from start to finish.

Key points: Each product has its own Process Flow. Any changes made by engineers must be rigorously verified because "one shot moves the whole body".

Recipe (Procedure / Formulation)

Explanation: Specific parameter settings performed on a specific device for a specific process step. For example, a recipe for one etching specifies gas flow, power, pressure, time, etc.

Key points: Recipe is the basic execution unit of the process, and its stability and accuracy are crucial.

Category III：Key Process Modules

This is the area of expertise of each unit process engineer, but as a newcomer, you need to understand what each module does.

Lithography

Photoresist / PR ：A chemical that is sensitive to specific light (e.g., DUV, EUV) and is applied to the surface of the wafer.

Mask / Reticle ：A quartz plate engraved with circuit graphics is a photo-etched "negative".

CD (Critical Dimension )：The thinnest line width in a circuit is a key measure of the advanced level of the process. We often use SEM to measure CDs.

Core task: "print" circuit design drawings onto the wafer.

Etch

Dry Etch ：Plasma is used for etching, which has good directionality and can engrave vertical steep sidewalls.

Wet Etch ：Corrosion using chemical liquids, low cost, but usually isotropic (sideways corrosion).

The core task: to accurately "carve" out unwanted layers of material based on the graphics left by lithography.Thin Film

CVD (Chemical Vapor Deposition)：A thin film is formed on the wafer surface through a chemical reaction.

0040-09094 CHAMBER 200mm

PVD (Physical Vapor Deposition)：Target atoms are "beaten" onto wafers by physical methods (such as sputtering) and are often used to deposit metals.

0020-70376 Degas Chamber

Core task: Grow or deposit various layers of materials on the wafer, such as insulating layers (Oxide, Nitride) or conductive layers (Metal).

Implant / Diffusion

Dose ：The total number of ions injected.

Energy ：Determines the depth of ion implantation.

Anneal ：A high-temperature heat treatment step used to activate the injected impurities and repair lattice damage.

Core task: Incorporate specific impurity atoms (such as boron and phosphorus) into the silicon lattice to change their conductive properties to form N-type or P-type semiconductors. This is the key to making the transistor PN junction.

4. CMP (Chemical Mechanical Planarization )

Core task: sand the surface of the wafer to an extremely flat surface like sandpaper.

Key takeaway: Why do you need flat? Because BEOL has to stack many layers, if the next layer is uneven, the lithography on it cannot be accurately focused, and the entire chip is useless. CMP is a key technology for enabling multilayer metal interconnects.

Category IV：Metrology & Analysis

These terms are about how we check if the job is done well.

Metrology

Explanation: Generally refers to all measurement behaviors in the production process, such as measuring film thickness, CD size, etc.

SEM (Scanning Electron Microscope )

Explanation: The "eyes" of our engineers. It is used to take high-resolution photos of microstructures on the wafer to check whether the graphics, dimensions, and topography meet the requirements.

Defect

Explanation: Anything that shouldn't be on the wafer, such as Particle, Scratch, Pattern issue, etc.

Key points: Specialized scanning devices check for defects after each critical step and generate a defect map. Analyzing these defects is an important task to improve yieldWAT (Wafer Acceptance Test )

Explanation: The "final exam" after the wafer has completed all the manufacturing processes. The test transistor in the test scribe line is used to obtain key electrical parameters such as Vth and Id_sat.

Bottom line: WAT data directly reflects the end result of our entire process. WAT floating (parameters out of specification) is the biggest headache for our PIE engineers, and we need to start an investigation immediately.

FA (Failure Analysis)

Explanation: "Autopsy" work performed when the chip fails or the WAT parameters are abnormal. Through various sophisticated physical and chemical means, we peel back the cocoon layer by layer to find the root cause of the problem.

Category V：Process Integration & Control

This is the core job of a PIE (Process Integration Engineer), which is concerned with how to "glue" all process steps together and ensure the health of the entire process.

Process Window

Explanation: It refers to the range within which a certain process parameter (such as exposure energy, etch time) can be changed, and within this range, the output results (such as CD, film thickness) can meet the specifications (Spec).

Key points: The wider the window, the more robust the process is and the greater the ability to resist various production fluctuations. One of our core goals in R&D and optimization is to find ways to "broaden the process window".

Process Margin

Explanation: Similar to the process window, but with more emphasis on the "safe distance" of the current operating point from the specification boundary.

Key points: When someone says "the margin of this process is very small", it means that it is very sensitive, and a slight fluctuation may produce scrap, which requires special attention.

3. DOE (Design of Experiments )

Interpretation: A scientific and efficient method of scheduling experiments to study the influence of multiple process parameters on the results.

Key Points: This is a "nuclear weapon" for engineers to solve complex problems. When faced with difficult yield problems or new processes need to be developed, we do not blindly trial and error, but systematically find the optimal combination of parameters through DOE. You will often hear "let's come to the next batch of DOE wafers".

4. TCAD (Technology Computer-Aided Design)

Explanation: Simulate the entire chip manufacturing process and the electrical behavior of the device on a computer.

Key points: This is a "virtual fab" that predicts the impact of process changes on device performance without using real wafers. It can greatly save R&D costs and time, and is an essential tool for advanced process research and development.

5. Scribe Line

Explanation: The division area between the chip (Die) and the chip. At the time of manufacture, we place structures dedicated to testing in this area.

Point: The WAT data you see is the test key in these Scribe Lines. They are the "sentinels" that assess the process uniformity and health of the entire wafer.

6. Dummy Pattern / Fill Pattern

Explanation: Graphics that are added to an empty area of the circuit to improve the uniformity of pattern density and have no real function.

Key takeaways: This is critical for CMP and Etch processes. Without Dummy, the grinding and etching rates in the sparse and dense areas of the graphic would be inconsistent (known as the Loading Effect), resulting in poor flatness and dimensional control.

Category VI: Advanced Module Terminology

1. Lithography & Etch

Overlay ：Measures the accuracy of the alignment of the front and rear lithography patterns. If the engraving is not accurate, the transistor cannot be formed correctly, just like when building a building, the second floor is covered from the outside of the first floor.

Selectivity：During the etching process, the ratio of the etch rate of the target material to the etch rate of the non-target material, such as photoresist or the underlying film.

Key points: The higher the selection ratio, the better the meaning of maximum protection of the underlying functional layer and the photoresist "mask" while carving through the target layer.

Profile / Taper Angle ：The morphology of the sidewall after etching. It can be vertical

(Anisotropic),It can also be tapered or even isotropic. Key points: Different applications require different profiles. For example, contact holes require vertical sidewalls to guarantee good filling, while some slope structures require specific angles.

OPC (Optical Proximity Correction )：The pattern is pre-distorted and deformed on the mask to compensate for the distortion caused by optical diffraction during lithography.

Takeaway: Without OPC, the rectangle you design may become dumbbell-shaped on the wafer. This is the key to guaranteeing graphic fidelity

2. Thin Film & Thermal

Step Coverage (Step coverage): The ratio of the thickness of the side wall of the step to the thickness of the flat surface when the film is deposited on a surface with uneven structure.

Key points: Poor step coverage can lead to metal fracture or insulation cavities in the connection holes, which is a reliability killer.

ALD (atomic layer deposition) technology is favored for its perfect step coverage.

Stress: Tensile or compressive stress present inside the film.

Key points: Excessive stress can cause wafer bending (Bow/Warp) and even cracking and peeling of the film. But we also use stress to improve device performance, which is called "strain engineering".

RTA (Rapid Thermal Anneal )：A heat treatment technology that can quickly raise the wafer to a high temperature and then cool it down quickly in a few tens of seconds.

Key points: RTA can achieve the same activation/repair effect compared to a few hours of treatment with a traditional furnace tube (Furnace) while effectively controlling the excessive diffusion of impurities, which is critical for size reduction.

Category VII：Yield, Defect & Analysis

1. Yield Excursion / Yield Crash

Explanation: Refers to a sudden or persistent deviation from the normal baseline in product yield(Baseline).

Takeaway: This is the most urgent alert in the fab. Once it occurs, an interdepartmental "Task Force" is immediately established to solve the problem.

2. D0 / Defect Density

Explanation: The number of defects per unit area. D0 is the core indicator to measure process cleanliness.

Key points: The higher the D0, the lower the yield. We are constantly working to minimize D0.3. Kill Ratio

Explanation: The probability that a particular type of defect will cause the chip to eventually fail.

Takeaway: Not all defects are fatal. A large size particle falls in the active zone, and the Kill Ratio may be close to 100%; A small defect in a non-critical area may have no impact. Analyzing the Kill Ratio helps us prioritize the most lethal defects.

4. Systematic vs. Random Defect

Explanation: Systemic defects are regular, recurring, and often associated with the design of masks, equipment, or specific process steps. Random defects are accidental and irregularly distributed, such as particles in the environment. Key points: The idea of solving the two is completely different. Systemic defects need to be solved from the root cause (such as modifying OPC and optimizing recipes); Random defects require improvements in equipment maintenance and the factory environment

5. In-line Inspection

Explanation: Inspect the wafer surface with equipment (such as KLA's scanner) immediately after a critical step in the production process, rather than waiting until all processes are complete.

Key takeaways: This allows us to detect problems early in their careers, intercept problematic wafers in time, and quickly locate problem processes to avoid batch scrap.

Category VIII：Equipment & Operations

1. MES (Manufacturing Execution System)

Explanation: Fab's "brain" and "nerve center". It tracks the real-time position of each lot, controls the equipment to execute the correct recipe, and collects massive production data.

Key points: Engineers use the MES system to give instructions, check data, and hold lots. You can't do without it every day.

2. PM (Preventive Maintenance )

Explanation: The work of equipment engineers regularly cleaning, maintaining, and replacing consumables on equipment.

Takeaway: Just like a car needs regular maintenance. High-quality PM is the basis for ensuring stable operation and reducing D0. The recovery of equipment status after PM is something that our process engineers need to closely monitor.

3. Hold Lot

Explanation: Due to the discovery of abnormalities (such as SPC OOC, measurement exceeding the standard, high defect), a lot is suspended in the current step through the MES system to prohibit it from continuing to tape out.

Key takeaway: This is the key action for stop loss. The Held Lot needs to be analyzed and dispositioned by the engineer to decide whether to release, scrap or rework.

4. OOC / OOS (Out of Control / Out of Spec)

Explanation: OOC refers to the data points on the SPC graph that exceed the control line (UCL/LCL), indicating that the process fluctuates, but the results may still be within specification. OOS means that the measurement result exceeds the engineering specification (USL/LSL), which means that the product is no longer conforming.

Key points: OOC is an early warning and needs to investigate the cause. OOS is an accident and usually requires an immediate hold lot.