【Semiconductor etching process】The soul of semiconductors teaches the etching process and the practice of engineers on defective rate problems from 0 to 1（CH7-CH8)

CH7. Structure of dry etching equipment

Components of the etching device

Pump = It acts to form and maintain the high vacuum state required for thin film etching

RF Generator =Power is applied to the injected gas, creating an energy source for the plasma

3.Chiller= Cooling the heat generated during the etching process to reduce film inhomogeneity and damage

4.Process Chamber = The reaction chamber where the etching is carried out maintains a certain pressure, where the gas reaction occurs and the reaction products are discharged through the exhaust pipeline

5.Gas Box= It has an MFC (Mass Flow Controller) device to regulate the gas flow and distribute the gas

6.Main Controller = Control all devices

Definition of vacuum

In a certain space, air molecules are removed below atmospheric pressure.

Reasons for the need for vacuum in semiconductor processes

In order to remove impurities in order to achieve the desired process results through a purification reaction and to increase production efficiency.

Mean Free Path, MFP

The average distance a particle travels before colliding with another particle.

Plasma Etching

The method of coupling the RF power supply to the anode – etch rate: Poly Si > SiN > SiO₂

Etching is performed by chemical reactions between free radicals and wafer samples

Utilization of F-gas plasma - isotropic

Reactive ion etching (RIE)

The RF power supply is connected to the cathode above the sample via a capacitorThe reactions involved in etching are not only free radicals, but also ion → chemical reactions + collision etching

Problem: Ions accelerated by DC bias can cause damage to the substrate

Features: Anisotropic etching by ion bombardment / High density patterns can be formed / Polymers are sometimes intentionally generated to achieve anisotropic etching

Ashing

Definition: Dry strip and wet removal of hardened due to processes such as dry etching, wet etching, or ion implantation

Photoresist (PR), Dry Ashing + Wet Strip is commonly used.

Types: PlasmaAshing / O₃ Ashing / High Frequency, Ultraviolet Degumming

• Plasma degumming

•① Cylindrical type - high production efficiency, but easy to cause damage

•② Monolithic type - high uniformity, but easy to cause damage

•③ Downstream - reduces damage

•Light/ozone degumming

•① Light degumming - no damage, no metal pollution and film deterioration

•② Ozone degumming – reduces damage

Notes: The photoresist must be thoroughly removed / removed from the wafer by a rinse process / must not damage the wafer surface or substrate

Proceed with the steps

Ashing after Ion Implant

2.Low Dose (≤E15) requirement = 1 step / high temperature / high degumming rate

3.High Dose (> E15) requirement = 2 steps / low temperature / low degumming rate

4.Ashing after Etch

5.Pre-Metal Etch Process Requirements = 1 step / high degumming rate (Si, SiO₂ etching, etc.)

6.Process requirements after metal etching = same as above (for metal etching)

CH8. Dry etching process

Types of dry etching

1.Types and overview of oxide (SiO₂) etching

•Process Name：SAC (Self Align Contact)

•Process requirements: ensure contact resistance/low voltage/high selection ratio

•Principle: When etching contact oxides, by increasing the inter-film selection ratio, when encountering nitride next to the gate, only the oxide is etched, resulting in the formation of contact holes as shown in Fig. 3

•Objective: To solve the problem of defining the limit of photo alignment when contacting holes below 0.5 μm

•Process Name: Contact Etch

•Process requirements: After the previous etching arrives, it must have a high selection ratio to withstand over etch.

•Process Name: IMD Etching(Inter Metal Dielectric)

•Process requirements: It is very important to remove the polymer to ensure that there is no resistance (resistance-free) / The presence of TiN caps in the underlying metal is also an influencing factor

•Critical dimension (CD) consistency is important for different locations and structures within the wafer

2.Poly Si, Eth(Gate)

Silicide Etching

Etching requirements: Good vertical etch profile/good selection ratio for oxides (>10)

Gate electrode etching requirements: good selectivity ratio with gate oxide and anisotropic

Polymer removal process

Heat-induced polymer deposition(Polymer depo)

 - The lower the temperature, the more severe the deposition

- The polymer remains gaseous and is removed from the process chamber by vacuum exhaust

Polymer deposition caused by temperature gradients

- When the temperature gradient (difference) is 0, the deposition is uniform

- The relatively cold parts are more deposited

- Polymer deposition can be controlled by increasing the temperature of the undesirable part and lowering the temperature of the desired deposited part

- Too high a temperature can cause the polymer to cure, causing problems

Polymer deposition caused by chamber structure

- Polymers are prone to residue in the edges and corners or crevices of the equipment structure

- The eddy or back-stream of the gas stream determines the polymer deposition location

- The surface roughness inside the chamber affects the degree and location of the deposition

- Example: TCP-9400 - Polymer deposition of the drive component close to the wafer, eddy current and reflux cause a large amount of foreign matter to form on the wafer → Adjust the structure by increasing the distance between the wafer and the drive part

 

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