Semiconductor And CMOS Processes

Semiconductor and CMOS Processes

Natural sand is rich in silica (SiO₂), from which high-purity monocrystalline silicon can be extracted to manufacture integrated circuits. Monocrystalline silicon has extremely high purity requirements, which need to reach more than 99.99999999% (i.e., 9 9s), and silicon atoms need to be arranged according to the diamond structure to form a crystal nucleus. When the crystal plane orientation of the crystal nucleus is the same, monocrystalline silicon can be formed; If the orientation of the crystal plane is different, polysilicon will be formed.

Both monocrystalline silicon and polysilicon can be used in the manufacturing of integrated circuits, among which monocrystalline silicon is mainly used to build silicon substrates, and polysilicon can be used to make components such as gates, polysilicon resistors or capacitors of MOS tubes.

As shown in Figure 1, the production process from sand to chip is as follows: first, quartz sand is used as raw material to prepare single crystal silicon - the silica content of quartz sand is higher than that of ordinary sand, and metallurgical grade silicon can be obtained after refining treatment; then purifying, refining and depositing metallurgical grade silicon to produce polysilicon; Through the drawing process, polysilicon can be converted into monocrystalline silicon ingots. Cut the single crystal silicon ingots into thin sheets to obtain wafers. A large number of integrated circuit dies can be made on each wafer, which are sliced, tested, and packaged to make integrated circuit chip (chip) products.

Intrinsic semiconductors

Intrinsic semiconductors refer to pure crystals that are free of impurity atoms and free from structural defects. Germanium (Ge) and silicon (Si) are both quadrivalent elements and are commonly used semiconductor materials. In intrinsic semiconductors, although the four valence electrons on the outermost layer of atoms can form covalent bonds with the outermost electrons of surrounding atoms, under the excitation of heat or light energy, the electrons in some covalent bonds may break free from the covalent bonds, and then form conductive band electrons and valence band holes, which are collectively called carriers. Because the two carriers in intrinsic semiconductors always appear in pairs and are in a state of thermal equilibrium, under the action of an applied electric field, these carriers can move directionally to form an electric current, so that the material has a certain conductivity, so this type of semiconductor is called intrinsic semiconductor.

If a certain amount of specific impurity atoms is added to the intrinsic semiconductor, it will be transformed into a non-intrinsic semiconductor. Among them, non-intrinsic semiconductors incorporated with pentavalent elements are called N-type semiconductors, and such pentavalent elements are called donor impurities; Non-intrinsic semiconductors incorporated with trivalent elements are called P-type semiconductors, and these trivalent elements are correspondingly called host impurities. Unlike the thermal equilibrium state of intrinsic semiconductors, the two carriers in non-intrinsic semiconductors are always in an unequilibrium state: the dominant carrier is called the majority carrier (referred to as the many), and the secondary carrier is called the minority carrier (referred to as the few). Since N-type semiconductors are doped with 5-valent elements, their momotrons are free electrons; P-type semiconductors are doped with trivalent elements, and their molecules are holes.

Inside the intrinsic semiconductor, the concentrations of the two carriers (conductive band electrons and valence band holes) in thermal equilibrium are the same, and this concentration is called the intrinsic carrier concentration. This concentration is not constant, but depends on the specific material of the semiconductor and the temperature at which it is located-the higher the temperature, the higher the concentration of the intrinsic carrier.

In non-intrinsic semiconductors, the concentration of most carriers (polypion) is roughly equivalent to the doping concentration of impurities, usually several orders of magnitude higher than the intrinsic carrier concentration. The concentration of a small number of carriers (few) is generally lower than that of intrinsic carriers, and there are also several orders of magnitude difference between the two. Therefore, compared with the multi-particle concentration, the oligoptonic concentration is extremely low, which is negligible in most computational and analysis scenarios.

The carrier produces a directional drift motion driven by electric field forces. In a weak electric field environment, a direct proportional relationship is satisfied between the average drift velocity v of the carrier and the electric field strength E, which is expressed as

(where the proportional coefficient μ is called the mobility of the carrier, which is measured in centimeters per volt second, i.e., cm/(V·s)).

This drift motion of the carrier can form a drift current, and the magnitude of the drift current is positively correlated with the carrier mobility. It should be noted that although the actual drift direction of holes and free electrons is opposite under the action of electric field force, the drift current direction formed by each of them is exactly the same, so the total drift current inside the semiconductor is equal to the superposition of the hole drift current and the free electron drift current.

When the strength of the applied electric field is the same, the larger the drift current density of the semiconductor, the stronger its conductivity. Further analysis shows that the drift current density is not only directly proportional to the mobility of the carrier, but also to the concentration of the carrier. Although the carrier concentration of intrinsic semiconductors is not zero and can produce weak drift currents under the action of electric fields, the multi-sub concentrations of non-intrinsic semiconductors are usually many orders of magnitude higher than the intrinsic carrier concentrations, which makes the drift current density of non-intrinsic semiconductors much larger than that of intrinsic semiconductors. Therefore, the drift current density of intrinsic semiconductors is usually negligible when calculating the drift current.

P-type and N-type semiconductors

Q- Due to the extremely small drift current density of intrinsic semiconductors, intrinsic semiconductors can usually be regarded as insulators compared to non-intrinsic semiconductors. Because of this, the semiconductor materials used in the actual manufacture of integrated circuits are non-intrinsic semiconductors. The conductivity of non-intrinsic semiconductors is closely related to the mobility μ of multiplons: the greater the mobility, the stronger the conductivity of the semiconductor, and the faster the device made on the semiconductor works.

The carrier mobility data for germanium (Ge) and silicon (Si) are shown in Table 2 (where free electron mobility is written as μn and hole mobility is written as μp). The free electron mobility μn of both Ge and Si is much greater than that of hole mobility μp, so N-type semiconductor devices perform significantly better than P-type semiconductor devices in key performance indicators such as gain, frequency characteristics, and driving capability.

As shown in Figure 2, when the N-type semiconductor and the P-type semiconductor are in close contact, a PN junction will form at the interface between the two. In the junction region, free electrons in the N region diffuse to the P region, while holes in the P region diffuse to the N region. After this diffusion motion occurs, an internal electric field is formed at the interface from the N region to the P region. As the strength of the internal electric field gradually increases, the final diffusion force and the internal electric field force reach an equilibrium state, and the diffusion motion stops. At this time, a region without free electrons and holes will form at the intersection interface, which is called the space charge region and is often called the depletion zone. If the electrodes are drawn out at both ends of the PN junction, a diode can be formed - the electrode from the P region is the anode, and the electrode from the N region is the cathode.

Applying voltage to both ends of the diode can break the original equilibrium between the diffusion force and the electric field force. If the applied voltage meets the cathode potential higher than the anode potential, the applied voltage will increase the internal electric field force, causing the carrier to still be unable to carry out diffusion motion - since there is no diffusion current, the diode is in a cut-off state. On the contrary, the applied voltage will weaken the internal electric field force, the carrier will start to diffuse again, and the diffusion current will be generated inside the diode, at which point the diode will enter the conduction state. This ability to switch on or off with the applied voltage makes the diode unidirectional conductive, which in turn plays a key role in the circuit. In the CMOS process, several types of PN junctions are formed, which can be used not only to manufacture diodes in integrated circuits, but also to achieve electrical isolation between devices in the reverse bias state.

The process of introducing 5-valent or 3-valent elements into semiconductors is called doping, and the doping process is commonly used by ion implantation. When the ion implantation concentration is low, it is lightly doped (expressed as N⁻, n⁻ or P⁻, p⁻); When the ion implantation concentration is high, it is he-doped (expressed as N⁺, n⁺ or P⁺, p⁺). Obviously, the conductivity of heavily doped semiconductors is better than that of lightly doped semiconductors.

When local heavy doping is carried out in a large area of light doping area, the light doped area is generally called the substrate, and the heavy doping area is called the diffusion zone (diffusion) or active (active). The type of semiconductor in the diffusion zone and the substrate can be the same (both N-type or P-type) or different (heteromorphism). In the CMOS process, there are two situations: homotype doping is mainly used to educate the electrode and realize the connection through ohmic contact, and special-type doping is mainly used to construct an isolation structure between the MOS device and the substrate.

Semiconductor devices need to be led out of the electrode through metal. When a semiconductor comes into contact with a metal, redoping allows electrons to tunnel through the contact barrier, resulting in low-resistance ohmic contacts that can be used to elicit electrodes. However, in the case of light doping, the contact resistance between the semiconductor and the metal is extremely large, and the electrode connection effect is not good, so it cannot be used to lead out the electrode. Therefore, to extract the electrode from the low-doping substrate, the substrate needs to be locally re-doped with isomorphism, and then the metal electrode is introduced.

As shown in Fig. 3, the profile structure of the N-well and the metal is connected by ohmic contact. N-traps are lightly doped N-type semiconductors that are often used as substrates and need to be connected to a power supply VDD. To achieve effective connection, isomorphic redoping is required in the N-well to form an N⁺ diffusion region, thereby contacting the metal to construct ohms. It should be noted that the silica (SiO₂) in Figure 3 is used to achieve insulation isolation between metal and semiconductor, and in order to form ohmic contact between the metal and the N⁺ diffusion region, holes need to be opened in the SiO₂ layer, which are called contact holes.

Since the injection of special-shaped ions can form PN junction diodes between the diffusion region and the substrate, multiple diffusion regions on the same substrate can be isolated from each other by the diode as long as the bias voltage is reasonably controlled so that the diode is always in the reverse bias state. As shown in Fig. 4, the diode isolation profile structure of the two P⁺ diffusion regions is shown in Fig. 4: the two P⁺ diffusion regions in the N-well form two independent diodes with the N-well, and the N-well is connected to the highest potential VDD through the N⁺ diffusion region, which can ensure that the two diodes are always in the reverse bias state, and then realize the diode isolation between the two P⁺ diffusion regions.

Similarly, if the P-type substrate is connected to the lowest potential GND, the diode isolation between multiple N⁺ diffusion regions can be achieved. Fig. 5 shows the diode isolation profile structure of the N-well process, which shows the diode isolation structure between the two P⁺ diffusion zones and between the two N⁺ diffusion zones. The substrate of the entire wafer in the figure is a P-type substrate, and the N-trap is made on top of the P-type substrate. Combined with the potential relationship in Fig. 5, it can be seen that the PN junction diode between the N-well and the P-type substrate is also in the reverse deflection state, which ensures the isolation between the N-well and the P-type substrate. This process, which only contains N traps and does not set P traps, is called N well process.

As shown in Fig. 6a, if two P+ diffusion regions are injected into the N-well, or two N+ diffusion regions are injected into the P-type substrate, the region between the two diffusion zones is defined as a channel, and the channel and the substrate are a whole. The substrate is referred to by the letter B, and the diffusion zones on both sides of the channel are represented by S and D, which are connected to the metal by contact holes. Make a metal electrode directly above the channel, which is denoted by the letter G. Combined with the voltage relationship applied in Fig. 6, it can be seen that the PN junction diode between the N-well and the P-type substrate is in the reverse bias state, and the diffusion zone on both sides of the channel and the respective substrate are also in the reverse bias state, so all S and D in the figure are not conducted. It should be noted that there are two separate sets of S, D, G, and B in the figure, using the same letters here, just to facilitate the subsequent naming of the MOS tube pins.

In Figure 6b, the channel between the two N+ diffusion regions belongs to a P-type substrate that is connected to GND. At this time, if a positive voltage V₁ is applied to G above the channel, the electric field generated between G and the channel will attract some electrons, which will fill the holes in the channel. If V₁ is high enough that electrons remain after filling the hole, the channel will change from P-type to N-type, and then connect the two N+ diffusion regions, so that S and D are conducted. When the voltage of V₁ drops to 0, the channel returns to P-type, isolating S from D again. Therefore, S and D are equivalent to the two ends of an electronic switch, and their on/off and disconnection are controlled by the voltage of G.

In the same way, the channel between the two P+ diffusion regions in the N trap in Fig. 6b is the N well, and the N well is connected to the VDD. At this point, a voltage V₂ below VDD is applied to G above the channel, and the electric field between G and the channel repels electrons in the channel. When V₂ is low enough, not only free electrons are repelled out of the channel, but also electrons in some covalent bonds, forming holes within the channels. In this way, the channel changes from N-type to P-shaped, connecting the two P+ diffusion zones and allowing S and D to conduct. When the voltage of V₂ rises again to VDD, the channel returns to N-type, isolating S from D again, so the structure is also an electronic switch controlled by G.

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CMOS

The diffusion zones on both sides of the channel are called Source (S) and Drain (D), and the electrode plate above the channel is called Gate (G), which together with the backgate (B) of the substrate constitute the MOS tube. The device composed of two N+ diffusion regions and their corresponding gates is called NMOS tubes, and the devices composed of two P+ diffusion regions and their corresponding gates are called PMOS tubes, and the symbols of the two are shown in Fig. 6c.

The gate material of early MOS tubes is aluminum, which belongs to the category of metal. The silica between the gate and the channel belongs to oxide. The channel belongs to the semiconductor. Combining the initials of the three English words Metal-Oxide-Semiconductor gives MOS (i.e., metal-oxide-semiconductor), which is why the MOS tube is named. It should be pointed out that in the actual process, the thickness of the silica layer below the gate needs to be less than that of other areas.

MOS tubes can be simply understood as electronic switches controlled by gate voltage: NMOS tubes turn on when the gate voltage is high, and PMOS tubes turn on when the gate voltage is low. As shown in Figure 7, the PMOS tube and NMOS tube are connected in series between VDD and GND, and the two gates are connected together as input port A, and the drains of the two MOS tubes are connected together as output port Y. When A is high, the NMOS tube is turned on, the PMOS tube is cut off, and the output Y is pulled down. When A is low, the NMOS tube is cut off, the PMOS tube is turned on, and the output Y is pulled up. As a result, A and Y form an inverse phase, and the circuit is called an inverter.

In the inverter shown in Fig. 7, because the PMOS tube is connected to the gate of the NMOS tube, and the gate voltage required for the two to be turned on is opposite, the NMOS tube and the PMOS tube will not be turned on at the same time, and there is no current flow between the power supply and the ground, which is equivalent to no static power consumption. In addition to the inverter, the NMOS tube and the PMOS tube can also form various other logic gates, which also have no DC power consumption in the static operating state. Due to the extremely perfect complementary characteristics of NMOS tubes and PMOS tubes, the circuit composed of the two is named Complementary Metal-Oxide-Semiconductor (CMOS).

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Although there is no direct flow between the power supply and the ground (i.e., no static power consumption) when the CMOS logic gate is at rest, during the logic gate state flip, the NMOS tube and the PMOS tube will have a short simultaneous conduction phenomenon, which will generate a certain dynamic power consumption. In addition, the process of charging and discharging load capacitors by logic gates also incurs power consumption. Since these power consumption are all related to the flipping of the logic gate, the higher the clock frequency, the greater the power consumption of the CMOS circuit; However, the clock frequency of modern large-scale integrated circuits is generally high, so solving power consumption and heat dissipation problems is still a difficult problem in CMOS integrated circuit design.

As the CMOS process continues to develop according to Moore's Law, the thickness of the silica layer between the gate and the channel continues to decrease, and the gate leakage phenomenon becomes more and more serious. This problem was not obvious before the deep submicron process stage, but after entering the tens of nanometers process node, gate leakage power has become the main source of total circuit power consumption. Before the deep submicron process stage, only clock gating is required to shut down the circuit; However, after the deep submicron process, the situation changes – in addition to shutting down the clock, the supply voltage needs to be reduced or the substrate voltage must be raised to minimize gate leakage power consumption. With the continuous expansion of the scale of integrated circuits, power consumption and heat dissipation have become design bottlenecks. Only through more technological innovation can we ensure the continuous advancement of Moore's Law and further improve the integration of chips.