What is CMP

0010-01712 5500 Tube Robot

0010-21631 A B Chamber Lid

Chemical Mechanical Polishing Technology in the Semiconductor Industry

The final polishing step is a combination of chemical etching and mechanical polishing, and this form of polishing is called chemical mechanical polishing (CMP). The first thing to do is to mount the wafer on a rotating bracket and lower it to the height of a pad, then rotate it in the opposite direction. Bedding is usually constructed of a cast and sliced polyurethane with a filler or material known as urethane-coated. Silicone (glass) slurries, such as potassium or ammonium hydroxide, suspended in relatively mild corrosives, need to be fed into the polishing pad.

The alkaline slurry is chemically reacted on the wafer to create a thin layer of silica surface. The mechanical polishing process of the pad removes the oxides in a continuous process. The high spots on the surface of the wafer can be removed by this step until an extremely flat surface is formed. If the surface of a typical semiconductor wafer extends to 10,000 feet (the length of a typical airport runway), what level of flatness would it be? The change in its surface will be less than or equal to plus or minus 2 inches.

In order to be able to achieve extreme flatness parameters, a series of combination conditions such as polishing time, pressure on the wafer and liner, rotation speed, slurry particle size, slurry feed rate, slurry chemistry (pH) and bedding material need to be controlled very standardly.

Chemical mechanical polishing is one of the technologies that has developed in this industry, and the creation of this key technology has made it possible to produce larger wafers. CMP is used in the wafer fabrication process to make the surface of the wafer flatter after a new layer is formed. In this application, the CMP process is the most critical technology used for planarization. A detailed explanation of this use of CMP will continue in the following sections.

Back treatment

In most cases, only the front side of the wafer can be manipulated by CMP technology. The back of the wafer may leave a rough or etched bright appearance. For some devices, the back side may undergo a special process that causes damage to the crystal, which is known as back damage. The damage to the back can spread further to cause the production of dislocated wafers up to the top layer. These dislocations can be introduced into the wafer during the wafer fabrication process as a mobile ion contamination trap. The phenomenon of trapping can be referred to as sampling (as shown in the figure below). Backside processes include sandblasting or polishing to deposit a layer of polycrystalline silicon or silicon nitride on the backside.

Polished on both sides

One of the common requirements for large diameter wafers is planar and parallel surfaces. Most manufacturers of 300 mm diameter wafers use double-sided polishing to achieve planar specifications of 0.25 to 0.18 μm in a 25*25 mm grid. The disadvantage is that all further processing must be done with a treatment technology that does not scratch or contaminate the backside.

Edge polishing

Edging is a mechanical process that gives a wafer a rounded edge (as shown in the figure below). During the manufacturing process, chemical polishing can further create minimized edges, which can cause the wafer to crack or be damaged, which in turn involves the nucleus of the dislocation line, which can propagate to chip wafers close to the edge.

Evaluation of wafers

Before packaging, the wafer (or sample) is checked for some parameters, such as those specified by the customer. Typical wafer specifications are illustrated in the figure below. The 300mm wafer in the figure below is a typical specification. The main concern is surface issues such as particles, stains, and haze. These problems can be detected by the use of high-intensity lamps or automated technology to detect the machine to be inspected.