Barrier Deposition in Chip Manufacturing

Why do you need a barrier layer?

In the copper interconnect process of chips, copper atoms are highly susceptible to diffusion to the surrounding insulating medium (such as SiO₂ or Low-K materials), resulting in a short circuit or leakage failure. To stop this diffusion, a nanoscale barrier layer must be deposited between the copper and the medium. Tantalum nitride (TaN) has become the mainstream choice due to its high compactness, anti-diffusion ability and electrical conductivity. However, as the process moves to sub-28 nm, the uniformity and coverage of the barrier layer face significant challenges.

 

Physical Vapor Deposition (PVD) Technology:

At the 22 nm and 14 nm nodes, PVD is still the core technology of barrier layer deposition, with the following advantages and innovations:

The ionized metal plasma PVD

The tantalum target is bombarded with high-energy ions, and the tantalum atoms are sputtered out and reacted with nitrogen to form TaN films. Re-sputter process. After the TaN is deposited, the surface of the film is bombarded with argon ions to redistribute the TaN at the bottom to the sidewall, significantly improving the through-hole coverage of the aspect ratio >5:1 (e.g., a 40% increase in sidewall coverage at the 32 nm node).

Process advantages
The deposition rate of TaN thin films (2-5 nm) can reach 10 nm/min, which is suitable for mass production. No carbon-based precursors are required to avoid carbon residue problems in the ALD process; The equipment is mature, and the cost of a single process is more than 30% lower than that of ALD.

Limitations

The bottom coverage of the deep hole is insufficient, and it needs to be combined with sputter clean to remove residual contaminants; In the linewidth below 10 nm, the step coverage rate of PVD (<50%) is difficult to meet the demand.

0040-02544 Upper Body, Dps Metal

Atomic Layer Deposition (ALD)
Although ALD is theoretically atomic-level accurate, it still faces multiple challenges in practical applications:

Process bottlenecks in ALD TaN

Precursor contamination: When using an organic tantalum source (e.g., Ta(NMe₂)₅) and ammonia (NH₃), carbon residues lead to an increase in film resistivity (3 times higher than PVD TaN); Steric hindrance effect: In structures with an aspect ratio of > 10:1, the precursor molecules cannot effectively diffuse to the bottom, resulting in discontinuity of the film. Low deposition rate: ALD grows only 0.1 nm in a single cycle, and it takes 50 cycles to deposit 5 nm films, which is 10 times longer than PVD.

Potential benefits and future applications
ALD enables thickness control of ±0.2 nm on the sidewall of 3D FinFETs; As the linewidth shrinks to 5 nm, ALD may be the only technology that meets the coverage requirements.

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Analysis of key process flows (taking 28 nm double Damascus structure as an example)

Chemical Clean
Purpose: To remove copper oxide and etch residues from vias.

Method: Nitric acid/hydrofluoric acid (HNO₃/HF) mixture solution corroded, followed by baking at 200°C to remove moisture.

Sputter Clean
Parameters: Soft argon ion bombardment (energy < 50 eV) to remove residual contaminants at the bottom and improve TaN adhesion.

TaN deposition and resputtering
PVD deposition: A 2 nm TaN layer is deposited, followed by argon ion resputtering, redistributing the bottom TaN to the sidewalls (from 60% to 85% coverage).

Tantalum (Ta) layer deposition
Function: Acts as an adhesion layer for the copper seed layer with a thickness of 1-2 nm to prevent copper from peeling.

(Cu Seed)Deposition
Process: PVD deposits a 300 nm copper layer to provide a conductive substrate for subsequent electroplating copper filling.