Analysis Of CV Measurement Technology Of Semiconductor Devices

Analysis of CV Measurement Technology of Semiconductor Devices

Essentials of the CV measurement principle

The principle of self-balancing bridge CV instrument
The device impedance is measured by the formula Zx=Ix/Vx:

Hc/Hp terminal: apply AC signal and DC bias, real-time monitoring of the voltage Lc terminal at both ends of the DUT: construct a virtual ground through the reference resistance Rr, and accurately calculate the current Ix=Rr· Advantages of VR: The high frequency band has strong stability and can cover the frequency band below 10MHzFigure 1: Simplified block diagram of a self-balancing bridge CV instrument

0010-21631 A B Chamber Lid
Comparison of mainstream connection methods

Methods	Peculiarity	Applicable scenarios
4PT four-wire method	High accuracy, independent current/voltage detection	Precise measurements in the laboratory
S-2T Shielded two terminal	Simplified cabling (2 ports) with error compensation	Mass production testing, integrated IV/CV joint testing

Figure 2：Adopt Shielded two terminal(S-2T)Connecting Method

Wafer-level testing pitfall avoidance tips

19-024277-01 Heater,8inch,6pcs

The On-Wafer CV measures three major sources of interference: chuck parasitic capacitance, leakage current, and ambient noise

Optimization Solution:

Wiring strategy: low-impedance terminal (CML) is connected to the gate to isolate chuck noise; Shorten the length of the S-2T cable (recommended < 30cm)

Parameter setting: signal level: ≥100mV (improve signal-to-noise ratio); Integration time: medium/long mode (sacrificing speed for accuracy); Frequency selection: 1kHz-100kHz low frequency band (to avoid parasitic effects)

Figure 3: Schematic diagram of the On-Wafer test

Introduction to the Keysight B1500A CV module

Hardware Solutions

MFCMU Module: Multi-Frequency Capacitance Measurement Unit (Single Slot Integrated) SMU Module: Dual-channel Precision DC Bias Source SCUU+GSWU Combination: Seamless Switching of CV/IV Measurements, Routing Error <0.1%

Figure 4: Schematic diagram of the SCCUU module and circuit

Software processes

WaferPro Express operates in three steps:
Create a test routine (define the stimulus applied on the DUT pin, there is a default routine optional), configure SMU bias (Vgs/Vds/Vbs multi-parameter linkage), set CV scan parameters (frequency/level/integration time, etc.)

MOSFET Capacitance characterization in practice

Analysis of key capacitance components

The following diagram shows the capacitance distribution in the MOSFET:

图5：MOSFET器件界面图

Cgc(Gate-channel capacitance)：C4+C1+C6(含交叠电容)
Cgb(Gate-substrate capacitance)：Dominant device characteristics under reverse bias

Cgg(Grid capacitance)：Fully evaluate the switching speed of the device

Cgd, Cgs(Gate and drain/source level capacitors)
Drain and source-level junction capacitance

Test configuration examples

Test Type	Connection Method	WaferPro Routine Set
Cgc_Vgs_Vbs
Cgb_Vgb_Vdb
Cgd_Vds_Vgs
Cgg_Vgs_Vds

Technology Trends

With the evolution of the third generation of semiconductor devices to high frequency and high voltage, CV measurement is facing two major upgrade directions:
Broadband measurement: Extended to high frequency bands above 100MHz, S-parameter testing is introduced. Dynamic CV Analysis: Investigate the migration of capacitive characteristics under switching transients