VLSI 2024, What Did The Chip Giants Talk About?

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The 2024 IEEE VLSI Technology and Circuits Symposium, which showcases cutting-edge R&D achievements related to semiconductor device process technology and integrated circuit technology, opened on June 16, 2024 (local time) in Hawaii, USA.

432-core RISC-V Floating-point Accelerator

There were 11 presentations in the field of circuit technology as highlights. Papers of interest are selected based on topics such as processor and memory. The initial topics were "Processors and System-on-Chips," "Machine Learning Devices and Accelerators," "Memory Technology," and "Digital Circuits, Hardware Security, Signal Integrity, and IO."

On the processor side, ETH Zurich, Stanford University and the University of Bologna have jointly developed a floating-point arithmetic accelerator based on the RISC-V architecture. It consists of 432 cores as dual chiplets, and two HBM2E modules with a storage capacity of 16GB are mounted on the same board. For template operations and sparse linear algebra operations. Up to 28.1GFLOPS/W of floating-point performance per power.

In the field of machine learning, the Korea Advanced Institute of Science and Technology (KAIST) and Samsung Electronics have jointly developed a memory computing accelerator () with built-in 1T1C unit DRAM. Compatible with machine learning models such as ResNet, BERT, and GPT-2. COMPUTING PERFORMANCE PER UNIT POWER IS UP TO 28.1 TOPS/W. It is assumed that improvements in SQNR (Signal Quantization-to-Noise Ratio) and improvements in power efficiency are achieved. The manufacturing process is 28nm. Built-in 27Mbit DRAM.

In terms of memory technology, Arm has developed SRAM macros for primary data caching, which operate at frequencies up to 7 GHz (No. 16-3). The SRAM unit is a 1R1RW system with 8 transistors. The manufacturing process is 3nm and the storage density is 11.2Mbit/mm². Regarding digital circuits, Seoul National University and Columbia University have jointly developed a low-power, high-precision end-to-end 10-keyword speech recognition system. Designed to be used to launch/control mobile devices with voice commands. Power consumption is as low as 5.6μW. The recognition accuracy rate is 92.7%.

Seizure Prediction SoC with Unsupervised Learning

The next topics are "Medical Biodevices/Circuits/Systems","Sensors/Imagers/IoT/MEMS/Display Circuits", and "Data Converters".

In the field of medical biology, UC Berkeley will report on the development of SoCs for predicting and classifying seizures. By implementing a classifier that uses unsupervised sequential learning for prediction, the silicon chip area is reduced to one-fifth of that of traditional models, and the power consumption is reduced to one-third of that of traditional models.

For sensors/imagers, Canon has developed a 1 megapixel SPAD (Single Photon Avalanche Diode) image sensor that can measure distance even at high illumination of 50k lux. By configuring a network that sends and receives emission information from surrounding neighboring pixels, it is possible to measure distances in a high-light environment.

In terms of data conversion, the results of the University of Southern California and MediaTek jointly developed a 16 Gsample/s high-speed time-domain analog-to-digital conversion (ADC) circuit, and the 10-bit high resolution was selected for the paper. It is equipped with a pipeline-by-step approximation time-to-digital conversion (TDC) circuit with delay change correction and delay offset background correction. The manufacturing process is 4nm CMOS process.

CMOS wireless transmit/receive circuit in the 110-170GHz frequency band used for 6G mobile communication terminals

The final topics are "Analog and Mixed-Signal Circuits", "Wired and Fiber Optic Transceivers/Fiber Interconnects", and "Wireless and RF Devices, Circuits and Systems".

On the analog side, Samsung Electronics has developed a Class D audio amplifier for mobile devices with a THD+N (Total Harmonic Distortion plus Noise) of 0.00086% and a PSRR (Supply Voltage Rejection Ratio) of 118 dB. The maximum output is 5.8W, and the maximum efficiency is 93.2% (load 8Ω).

In terms of interconnection, TSMC has developed ultra-high-speed communication links between three-dimensional stacked silicon chips. Compute chips using 5nm FinFET technology and SRAM chips using 6nm technology are stacked together to form a communication link of 16Gbit/s per channel using the PAM-4 method at a pitch of 9μm. The number of transmit and receive links is 80 lanes. The communication speed per unit area (1 square millimeter) reaches 17.9 Tbit/s.

Intel's research on a 4-channel optical receiver circuit at 50 Gbit/s per channel (NRZ signal) was also selected as a noteworthy paper. Detachable fiber optic connectors, photodiodes, transimpedance amplifier (TIA) ICs, and receive data path ICs are all housed in the same package.

Tokyo Institute of Technology has developed a D-band (110 GHz to 170 GHz band) CMOS wireless transmitter/receiver circuit for next-generation (6G) mobile communication terminals. The 4-channel x 4-antenna MIMO (Multiple-Input Multiple-Output) communication is configured with a transmit/receive circuit of 200Gbit/s per lane, achieving an overall communication speed of 640Gbit/s.

Intel 3 Process, 2.5D Package Improved Foveros, and More Released

In the field of device/process technology, 5 projects are from "the latest and next-generation device/process technology for CMOS logic", 4 projects are from "next-generation memory technology", and 1 project is from "all-oxide material" transistor technology, and a total of 11 papers were selected as noteworthy papers, one of which is from "Performance Evaluation of Angstrom Generation PPA with Thermal Effects in Consideration".

"The Latest Next-Generation Device/Process Technology for CMOS Logic" includes a technical overview of Intel's cutting-edge mass production process "Intel 3" and Intel's 2.5-dimensional (2.5D) packaging technology "Foveros". The results of the development of the creation of high-density MIM capacitors were selected as a monograph.

In addition, Samsung Electronics (hereinafter referred to as Samsung) has 3D stacked transistor (CFET) technology with self-aligning direct backside contact and backside gate contact, and IBM Research's 2nm nanosheet FET backside power supply technology (which has also been selected for the miniaturization technology of two-dimensional transition metal disulfide (MoS2) channel transistors developed by TSMC and other joint research teams and TSMC.

Word-line air-gap isolation supports 3D NAND flash expansion

Next, among the next-generation memory technologies, Micron Technology's (hereinafter referred to as Micron's) 3D NAND flash cell thinning technology and Micron's fine transistor technology for ferroelectric non-volatile DRAM, SK hynix's Selector-Only memory (SOM) technology, and the ferroelectric non-volatile SRAM technology of a joint research group including Sony Semiconductor Solutions were selected as noteworthy papers.

According to reports, the 3D NAND flash cell thinning technology developed by Micron Technology introduces an air gap in the interlayer insulation film between the stacked word lines to reduce the parasitic capacitance of the word lines, and separates the charge capture area for each cell to suppress interference between adjacent cells.

Microtransistor technology for ferroelectric non-volatile DRAM developed by Micron Technology. Dual-gate thin-film transistor technology enables a small cell-selective transistor with a size of 4F2 (F2 is the square of the design rule).

SK hynix developed Selector Memory Only (SOM) technology and fabricated an array of memory cells with a half-pitch of 16 nm at the intersection of the memory cells, which is sufficient for SOM.

The ferroelectric non-volatile SRAM technology, developed by a joint research group including Sony Semiconductor Solutions, produced a 16Kbit non-volatile SRAM macroprototype using a 1T1C cell system with a cell-selective transistor and a HZO-based ferroelectric capacitor. 100% manufacturing yield was achieved using 130nm technology.

The ferroelectric non-volatile SRAM technology, developed by a joint research group including Sony Semiconductor Solutions, produced a 16Kbit non-volatile SRAM macroprototype using a 1T1C cell system with a cell-selective transistor and a HZO-based ferroelectric capacitor. 100% manufacturing yield was achieved using 130nm technology.

In the category of "Transistor Technology for All Oxide Materials", the 3D vertical integration technology of indium oxide (In2O3) materials by the joint research team of Purdue University and Samsung was selected as a noteworthy paper. Vertical transistors consist of thin-film channels made of indium oxide and thick-film gate electrodes. The film is formed using atomic layer deposition (ALD) technology.

In the "Performance Evaluation of the Performance of Angstrom Generation PPA Performance Considering Thermal Effects", a monograph was selected. The PPA of 10A generation (1 nm generation) nanosheet FETs and 5A generation (0.5 nm generation) monolithic complementary FETs (CFET) were evaluated.