What is Supervia technology? What are its functions?

As semiconductor processes advance to 3nm and more advanced nodes, traditional interconnect structures face challenges such as overcrowded metal layers and increased resistive-capacitive (RC) delays. To address this challenge, the industry has introduced a technology called Supervia .

Technical Definitions and Principles

Supervia is a dual damask-compatible self-aligned structure whose core feature is direct cross-layer connectivity. While conventional vias can only connect adjacent metal layers (e.g., Mx to Mx+1), Supervia allows skipping intermediate layers and directly connecting metal layers to non-adjacent layers (e.g., Mx directly to Mx+2). Because it needs to penetrate more insulating layers, this via has an extremely high aspect ratio, typically exceeding 10, and sometimes reaching 13 or higher. Supervia can coexist with conventional vias in the same design, functioning where a "faster jump" is required.

Technological advantages and performance improvements

Supervia delivers significant improvements in resistance and capacitance performance. Compared to conventional stacked vias with equivalent cross-sectional area, Supervia reduces vertical path resistance by approximately 40%, thanks to the reduction of multiple interface barrier layers in stacked vias. In terms of capacitance, Supervia reduces the parasitic capacitance of the intermediate metal layer by approximately 10% to 16%. Related experimental simulations show that Supervia's capacitance is 10% higher than that of regular stacked vias, indicating a positive impact on RC delay issues. Furthermore, by "bypassing" the intermediate metal layer, Supervia alleviates routing congestion in that layer, freeing up more space for horizontal routing. Regarding PPA (performance, power, area) optimization, studies show that Supervia can reduce core area by approximately 3.3%, power consumption by 3.2%, and improve signal timing.

Key application scenarios

Supervia is of significant value in standard cell miniaturization and power distribution networks. In terms of cell height scaling, conventional technologies typically have 7 to 12 tracks in standard cells, which can be reduced to 6, 5, or even 4.5 tracks using scaling boosters. Supervia is an essential tool for scaling down to 4.5 tracks, reducing line congestion in high-density routing and relaxing secondary design rules such as tip-to-tip. In buried power rail (BPR) architectures, Supervia is expected to become a critical component. Conventional power rails are located in the middle of the chip (Mint and M1 layers), occupying significant space and obstructing pin access. By burying the power rails in the front-end process, high aspect ratio Supervia is needed to deliver power to deeper power lines, thereby improving power efficiency and reducing IR drop.

Manufacturing Challenges and Future Prospects

Manufacturing high aspect ratio Supervias faces several process challenges. The IMEC team and its partners have produced the first samples using a dual-damascus-compatible self-aligned integration scheme (including photolithography, etching, and metallization steps), reducing the insertion cost of standard CMOS interconnect processes. However, these Supervias do not yet fully meet all technical specifications, presenting challenges such as non-uniform landing, via height consistency, and hard mask selectivity. Furthermore, the ultra-high aspect ratio makes traditional copper plating processes prone to voids, prompting the industry to explore alternative materials such as ruthenium (Ru) or cobalt (Co). Additionally, existing standard design tools do not yet support this structure, requiring specialized online monitoring metrology. Nevertheless, in the long term, enabling Supervia structures will help achieve the area scaling requirements of advanced technology nodes at 3nm and below.