One chip, three personalitie: How BCD technology integrates CMOS, DMOS, and BJT

In the world of power management chips, there's a technology hailed as the "Swiss Army Knife"-the BCD process. BCD is actually an abbreviation for three types of semiconductor devices: Bipolar Transistor (BPT), CMOS (Complementary Metal-Oxide-Semiconductor), and DMOS (Double-Diffused Metal-Oxide-Semiconductor). Why cram these three devices into a single chip? What roles do they each play? What are the differences in their manufacturing processes? Today, we'll disassemble this amazing "three-in-one" chip.

 

Why "three-in-one"?
Before the advent of BCD, engineers designing power supply chips often had to combine multiple chips from different processes: a bipolar chip to process analog signals, a CMOS chip for logic control, and a DMOS chip to drive high current. This approach was not only bulky and costly, but the connections between different chips also created parasitic effects, impacting performance and reliability.

The core concept of BCD technology is to integrate these devices with different "personalities" onto a single chip, allowing them to perform their respective functions and work together. This is like building a team: someone organizes the offense, someone is responsible for defense, and someone is the one who scores the goal.

Three Devices, Three Missions
: CMOS: The "Brain" of the Chip.
CMOS is responsible for logic control and digital signal processing. In modern BCD chips, the CMOS portion typically occupies the largest area, used to implement functions such as digital interfaces, timing control, and protection logic. CMOS's advantages are extremely low power consumption and high integration, easily enabling the implementation of complex algorithms and state machines.
In BCD processes, the CMOS portion typically employs mature technologies such as standard shallow trench isolation, polysilicon gates, and self-aligned silicides. To accommodate high-voltage environments, CMOS devices with varying gate oxide thicknesses are often provided: thin gate oxide for low-voltage logic (1.8V or 5V), and thick gate oxide for I/O circuits interfacing with high-voltage domains.
BJT: Precise "Analog Masters."

Bipolar transistors (usually NPN or PNP) excel at processing analog signals. They possess extremely high transconductance, low noise, and excellent matching characteristics, making them core components of analog circuits such as bandgap references, operational amplifiers, and comparators. Especially in scenarios requiring high-precision voltage references or temperature detection, the "temperature coefficient" characteristic of BJTs is difficult for CMOS to replace.

In BCD technology, BJTs are typically "parasitic" or "additional" structures-built using existing well and diffusion regions from CMOS or DMOS processes, rather than adding complex processes. A common approach is to use N-wells on a P-type substrate to form vertical NPN transistors, or P-wells to form lateral PNP transistors. While the performance of these BJTs is not as good as devices from pure bipolar processes, it is sufficient for the requirements of power management chips.

DMOS: A Powerful "Power Switch"

DMOS is the "strongman" of BCD chips, responsible for withstanding high voltage and conducting large currents. It is commonly used as a power transistor in power chips, such as high-side and low-side switches in DC-DC converters, and lithium battery protection transistors. The core indicator of DMOS is its on-resistance-the lower the resistance, the lower the conduction loss and the less heat generated by the chip.

In BCD technology, DMOS is mainly implemented in two ways:

LDMOS: Lateral structure, where current flows laterally on the chip surface. The advantages of LDMOS are good compatibility with CMOS processes, ease of integration, and voltage ratings ranging from 20V to 700V. Its withstand voltage capability is mainly determined by the length of the drift region between the channel and the drain. The longer the drift region, the higher the withstand voltage, but the on-resistance will also increase.

VDMOS: A vertical structure where current flows perpendicularly to the back of the substrate. VDMOS has lower on-resistance and higher current capability, but requires special processes such as back-side thinning and metallization, making integration difficult. LDMOS is the mainstream choice for smart power chips.

The challenge and wisdom of process convergence
lies in fabricating three distinct devices on the same wafer, which is not simply a matter of layering. The core wisdom of BCD process lies in using a single process flow to simultaneously meet the needs of three devices: device requirements, core process requirements, and process trade-offs.
CMOS's thin gate oxide, shallow junction, and low thermal budget require high-temperature annealing to activate impurities, which conflicts with BJT's deep junction; BJT's deep junction, high-concentration emitter region, and long high-temperature process can reuse CMOS's well region and source/drain implantation, eliminating the need for additional photolithography layers; DMOS's drift region, field oxide layer, and thick gate oxide require dedicated photolithography layers to define the drift region doping, increasing the process steps.
A typical BCD process flow first creates deep wells and buried layers (preparing for BJT and DMOS), then performs high-voltage drift region implantation, followed by CMOS's wells and gates, and finally completes source/drain implantation and contact vias. The entire process requires multiple photomasks, making it more expensive than pure CMOS, but far less expensive than packaging three chips together.

Applications and Future of BCD:
After nearly 40 years of development, the BCD process has evolved from the initial 5V/10A to the most advanced 120V and even 700V and above, with feature linewidths advancing from 3 micrometers to 90 nanometers or even smaller. Today, BCD chips are ubiquitous: fast charging adapters for mobile phones, automotive power management, motor drives, LED lighting, battery protection boards… almost every scenario requiring "intelligence + power" has its presence.

With the rise of electric vehicles and Industry 4.0, BCD technology is evolving towards higher voltages, higher power density, and smaller linewidths. Future BCD chips may integrate a complete power management system-including digital control, analog sensing, and power execution-on a single silicon wafer the size of a grain of rice, truly achieving "one chip for everything."

In conclusion
, the charm of BCD chips lies in their ability to allow three distinct devices to coexist harmoniously on the same silicon chip. CMOS handles the thinking, BJT handles the sensing, and DMOS handles the execution-these three work together to form the complete intelligence of a power management chip.