TSV Key Interface Materials and Processes

TSV Manufacturing Technology

In TSV manufacturing technology, it includes both through-hole etching and insulation related content in TSV manufacturing technology.

In addition, the three major links of TSV manufacturing: barrier layer, seed layer and Cu filling also determine reliability and cost.

This article is described as follows:

Adhesion layer and diffusion barrier layer

Seed layer

Conductive material filling

Adhesion layer and diffusion barrier layer

In the TSV manufacturing process, the adhesion layer and diffusion barrier layer are the key functional interfaces between the metal Cu column and the dielectric layer, and their material selection and deposition process directly determine the long-term reliability and process integration difficulty of the device.

Unlike planar interconnects, TSV's high aspect ratio structure places special requirements on the barrier layer: in addition to excellent Cu diffusion blocking ability, it is also necessary to solve the problem of conformal deposition in deep pores while balancing the stress of the film to avoid cracking or peeling. At present, the mainstream material system is dominated by tantalum (Ta)/tantalum nitride (TaN) and titanium (Ti)/titanium nitride (TiN), among which Ta-based materials have become the preferred scheme for high aspect ratio TSV due to their low resistivity (~20μΩ·cm), high step coverage ability and electromigration resistance. Ti-based materials have the advantages of strong adhesion to the SiO₂ dielectric layer (peel strength >5J/m²) and low stress (<100MPa), which are suitable for scenarios with strict mechanical reliability requirements.

The core function of the diffusion barrier layer is to block the penetration of Cu atoms into the silicon substrate - the diffusion coefficient of Cu in Si is as high as 10⁻¹⁴cm²/s. Therefore, the blocking layer needs to meet multiple performance indicators: firstly, amorphous structures (such as TaN) can eliminate the grain boundary diffusion path and achieve effective blocking at sub-10nm thickness; Secondly, in TSV with a depth-to-width ratio of more than 20:1, the barrier layer needs to be continuously covered by sputtering or MOCVD process, among which magnetron sputtering combined with cylindrical target technology can increase the step coverage to more than 95%. In addition, thin film stress control is crucial – intrinsic stress arises from lattice mismatch (e.g., stoichiometric deviation between Ta and N during TaN deposition), while thermal stress is caused by the difference in thermal expansion coefficient between metal (CTE~8ppm/K) and silicon substrate (CTE~3ppm/K), and the total stress needs to be reduced to less than 150MPa through process parameter optimization (e.g., sputtering power, substrate temperature).

It is worth noting that there is a significant difference in the demand for barrier layers between TSV and planar interconnects: in planar interconnects, the thickness of the barrier layer at the 65nm node is 10nm, which accounts for 35% of the interconnect section, forcing the industry to develop ultra-thin barrier layers (such as Ru-based materials); Due to the large cross-sectional size (diameter >1μm), the thickness of the barrier layer can reach the order of 100nm, and there is no need to overcompress the thickness, but instead focus on the conformity ability and adhesion optimization in the deep hole. For example, the NH₃ modulated sputtering process can introduce nitriding reactions during TaN deposition to improve the binding energy with the SiO₂ dielectric layer while reducing the sidewall roughness to less than 0.5nm.

In terms of industry dynamics, the atomic layer deposition (ALD)-TaN process recently developed by IMEC achieves uniform coverage of the TSV inner barrier layer with a depth and width ratio of 30:1 through cyclic alternating precursor pulses (Ta(NMe₂)₅ and NH₃), with a thickness deviation of <2%; The new ionized sputtering technology launched by Applied Materials reduces the resistivity of TaN films to 25μΩ·cm, which is 30% higher than the traditional process. In addition, for GaN and other wide bandgap semiconductor TSV applications, the low-temperature (<200°C) TaN deposition solution developed by Tokyo Electron has passed the -55~150°C thermal cycling test, providing a reliable solution for third-generation semiconductor 3D integration.

Seed Layer

In the TSV manufacturing process, the seed layer is the key conductive interface between the plating Cu column and the diffusion barrier layer, and its material selection and deposition quality directly determine the reliability of the plating filling and the electrical properties of the device. Unlike planar interconnects, TSV's high aspect ratio structure places special demands on the seed layer: in addition to low resistivity and good crystal orientation control, it also needs to solve the problem of continuous coverage in deep holes while balancing film stresses to avoid cracking or peeling. At present, the mainstream material system is dominated by cobalt (Co), ruthenium (Ru) and copper (Cu), among which Co has become the preferred solution for high aspect ratio TSV due to its high adhesion (peel strength >3J/m²) and low stress (<50MPa) with the TaN barrier layer. Ru-based materials, on the other hand, have high conductivity (~7μΩ·cm) and anti-electromigration characteristics, making them suitable for high-frequency application scenarios.The core function of the seed layer is to provide a uniform cathode potential for the plating Cu and control the crystal orientation of the plating to reduce stress. In planar interconnects, the thickness of the blocking layer needs to be compressed to less than 2.4nm at the 32nm node, forcing the seed layer to develop towards ultra-thinning. However, due to the large cross-sectional size (diameter > 1μm), the thickness of the seed layer can reach the order of 100-200nm, which does not need to be over-compressed and focuses on the continuous coverage ability in the deep hole. For example, when using the physical vapor deposition (PVD) process, TSVs with a depth-to-width ratio of more than 20:1 are prone to the absence of the bottom seed layer or discontinuity below the spike, and the step coverage rate needs to be increased to more than 90% through process optimization (such as tilt angle deposition and multi-target collaborative sputtering).

It is worth noting that there is a significant difference in the requirements of the seed layer between TSV and planar interconnect: in planar interconnect, seedless layer plating technology has begun to be explored below the 45nm node, which simplifies the process step by 30% by directly depositing Cu on the surface of the TiN barrier layer; However, the mass production process of TSV still needs to rely on the seed layer to ensure the stability of the plating, especially when the aspect ratio exceeds 30:1, and the seed layer enhancement technology (such as chemical mechanical polishing (CMP) repair before electroplating) becomes a necessary means.

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Conductive material filling

In the TSV manufacturing process, conductive material filling, as the core link to achieve vertical interconnection, has always ranked first in terms of technical difficulty and cost. With the evolution of 3D integrated circuits to smaller nodes (such as below 3nm), the TSV diameter has been compressed to 0.8-1.6μm, and the aspect ratio has exceeded 20:1, which puts forward the ultimate requirements for the filling process. The current mainstream solution is still dominated by electroplating copper (Cu), but its process complexity far exceeds that of the traditional Damascus process - it is estimated that Cu plating costs more than 40% of the total manufacturing cost of TSV, and the filling time is up to several hours, becoming a bottleneck in production capacity.

The core challenge of blind hole plating lies in the physical limitations caused by the high aspect ratio: first, the ion transport in the deep hole is blocked, and the Cu²⁺ concentration decreases gradiently from the opening to the bottom, resulting in insufficient deposition rate at the bottom and easy to form cavities or gaps. Secondly, the seed layer of PVD deposition is prone to discontinuity when the aspect ratio exceeds 5:1, which further aggravates the plating defects. In addition, poor surface wettability leads to bubble retention, concentrated current density at the opening causes "mushroom head" bulge, and a saucer-shaped pit is formed in the central area, which takes more than 30% additional time for subsequent CMP. To solve these problems, the industry adopts a multi-additive system (such as Enthone's PW1000) with pulsed reverse plating to achieve "bottom-up" filling by suppressing the deposition rate at the opening. At the same time, vacuum pretreatment and ultrasonic-assisted wetting technology can increase the bubble removal rate inside the blind hole to 95% to ensure uniform penetration of the plating solution.

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As a supplementary scheme, through-hole electroplating effectively avoids the problem of ion transport in deep vias by converting blind vias into through-holes and using transverse deposition sealing and unidirectional filling. Although this process requires additional wafer thinning and double-sided deposition steps, it can achieve a non-cavity filling with a depth-to-width ratio of more than 30:1 and reduce the dependence on plating solution additives. For example, the bidirectional plating equipment developed by Applied Materials, combined with through-hole sealing technology and dynamic current regulation, reduces filling time by 40% while controlling the thickness of the over-plating layer within 2 μm, significantly simplifying the CMP process.