The evolution of transistor technology in chips

If you take apart a smartphone or a computer, the core component is a chip the size of a fingernail cap.

The performance of a chip largely depends on the sophistication of the billions of "transistors" inside it. Transistors are like miniature electronic switches, controlling the "on" and "off" of current to achieve computing and storage.

From "Planar" to "Three-Dimensional": The Three Structural Revolutions of Transistors

Phase 1: Planar transistors (circa 2000)
At the beginning of the 21st century, chips used planar transistors. Think of it as a "gate" on a flat ground, with current flowing horizontally across the silicon surface. As the technology evolved, engineers introduced high-K dielectric layers and metal gates, which effectively reduced current leakage and enabled chips to operate at lower power consumption.

Phase 2: FinFETs (around 2011)

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When planar structures are difficult to shrink further, FinFETs (FinFETs) take the stage. It changes the conductive channel from "lying flat" to "erect", like pieces of fish fins standing on the surface of silicon. This design greatly enhances the gate's ability to control the current, allowing the chip to operate efficiently at a smaller size, and also promoting the rapid improvement of mobile phone and computer performance.

Phase 3: GAA nanosheets (around 2025)

In order to continue to reduce the size, gate-all-around (GAA) nanosheet technology has emerged. It uses multiple layers of horizontally stacked silicon nanosheets as conductive channels, and the gates are surrounded by channels from all sides, which has stronger control capabilities than FinFETs. This technology has been applied in advanced processes of 3nm and 2nm, marking the official entry of transistors into the "nanosheet era".

Future prospects: breakthroughs in stacking and 2D materials

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CFET: Next-Generation Technology Stacked Up (After 2030) When floor plans struggle to accommodate more transistors, engineers begin to "move upwards." Complementary field-effect transistors (CFETs) stack N-type and P-type transistors vertically together, significantly increasing transistor density per unit area of the chip while optimizing circuit layout and energy efficiency.