The basic manufacturing process of CMOS integrated circuits

 CMOS (Complementary Metal-Oxide Semiconductor) technology has developed into a mainstream process technology for semiconductor manufacturing since it was proposed by Wanlass and Sah in 1963. With the continuous development and improvement of key technologies such as local oxidation process of silicon, ion implantation technology, and lithography technology, the CMOS process has been widely used, and it follows Moore's law to continuously reduce the feature size and improve the integration.

The basic manufacturing process of CMOS integrated circuits

Front End

In the process of 0.18μm and below, the front-end process of the CMOS integrated circuit mainly forms the source-drain region of the device. Isolation method: 0.18μm or more: Isolated by local oxidation (LOCOS). 0.18μm and below: Shallow trench (STI) isolation is used to reduce the parasitic capacitance of the isolated area and improve the circuit performance.

Trap formation: In the 0.18μm process, the well uses retrogradewell technology to optimize device performance.

Back End

The back-end process completes the metal interconnect of the device.

Interconnect material:

more than 0.18μm: mainly use metal aluminum as interconnect material. 0.18μm and below: Although aluminum can still be used for interconnects, copper is mostly used as an interconnect material to reduce resistivity and improve circuit performance. Interconnect processes: including the formation of multiple layers of metal wiring and vias, as well as metal-silicon contact.

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Simplified steps for 0.18 μm CMOS process

1.Substrate preparation: Select the appropriate silicone substrate for cleaning and pretreatment.

2.Oxide growth: A thin oxide layer is grown on the substrate to act as a masking layer for subsequent processes.

3.Lithography and etching: Patterns are formed using photolithography and transferred to substrates through the etching process.

4.Ion implantation: According to the requirements of the device, different types of ion implantation are carried out to form source-drain areas and traps.

5.Annealing: The injected ions are annealed to restore lattice damage and activate impurity atoms.

6.STI Isolation: Shallow grooves are etched in the area to be isolated and filled with materials such as silicon oxide to form an isolation zone.

7.Metal interconnect: Multiple layers of metal wiring and vias are formed to complete the metal interconnect of the device.

8.Passivation & Encapsulation: A passivation layer is formed on the surface of the device and encapsulated to protect the device and improve reliability.

0.18μm CMOS Front End Process

Formation of active zones

Deposition of liner oxide layer and silicon nitride layer: On a P-type silicon substrate or P-type epitaxial layer, a layer of silicon dioxide (SiO₂) is first grown by thermal oxidation as a liner oxide layer to relieve the stress between the subsequent silicon nitride (Si₃N₄) layer and the silicon substrate. Next, a layer of silicon nitride is deposited as a hard mask layer for subsequent etching steps.

Lithography & Etching: Exposure and development are performed using 1 lithography plate to remove photoresist from isolated areas of the device. Subsequently, silicon nitride, liner oxide, and part of the silicon that are not covered by the photoresist are removed by wet or dry etching, forming a preliminary structure of shallow groove isolation (STI).

Thermal growth and planarization of silica: After the photoresist is removed, a layer of silica is grown at the bottom and side walls of the shallow groove by thermal oxidation, called Roundingoxide, which is used to smooth the sharp corners of the bottom of the shallow groove to reduce the reduction of breakdown voltage and the generation of leakage. Next, a layer of silica is deposited and densified using low-pressure vapor deposition (LPCVD). Finally, a planarization process is carried out by means of chemical mechanical polishing (CMP) to ensure the smooth progress of the subsequent process.

Removal of silicon nitride and growth of the final oxide layer: After the silicon nitride layer and part of the silica layer are removed, a layer of silicon dioxide is grown at 900°C as a barrier layer for subsequent ion implantation.

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Formation of N-traps and P-traps

Formation of N-traps: Exposure and development using 2 lithography plates to remove the photoresist in the N-trap area. Subsequently, a high-energy high-dose phosphorus (P) ion is injected to form an N trap. Arsenic (As) is then injected at a lower energy to prevent penetration between PMOS sources and drains. Finally, a low-energy injection of As is used to regulate the turn-on voltage of the PMOS. This distribution of energy and dose from high to low creates the so-called retrogradewell. Formation of P-traps: After the photoresist is removed, lithography of the P-traps is performed using 3 lithography plates. Subsequently, a high-energy, high-dose boron(B) ion is injected to form a P trap. Next, B is injected at a lower energy to prevent penetrations between NMOS sources and drains. Finally, a low-energy injection B is used to regulate the turn-on voltage of the NMOS.

Gate formation

Gate oxide growth and polysilicon deposition: After the formation of the N-trap and P-trap, the oxide layer is removed and the wafer is cleaned. Then, the thermal growth gate oxide layer is held at 800 °C. Next, a layer of polysilicon is deposited as the gate material.

Gate lithography and corrosion: Gate lithography is performed using a 4-lithography plate, and unwanted polysilicon is removed by dry etching to form a gate and polycrystalline interconnect of the device.

Formation of light doping source drain (LDD).

Formation of NMOSLDD: After gate formation, polycrystalline oxidation is carried out and a layer of silica is thermally grown on the gate polycrystalline. Lithography of NMOSLDD was performed using a 5-lithography plate, followed by the implantation of low-energy As ions to form a lightly doped source-drain region (NLDD) of NMOS.

Formation of PMOSLDD: After the photoresist is removed, photolithography of PMOSLDD is performed using 6 lithography plates. Next, low-energy B ions are injected to form a lightly doped source-drain region (PLDD) of PMOS. Since B diffuses faster than As, the injection energy of PLDD is lower than that of NLDD.

The production of Spacer

Deposition and Corrosion: A layer of TEOS (tetraethoxysilane) is deposited on the disc as a precursor to the Spacer. This is followed by isotropic dry corrosion, which retains the TEOS on the side wall of the gate polysilicon to form a Spacer.Rapid Thermal Annealing: High-temperature rapid thermal annealing (RTA) is performed on the injected LDD to activate the injected impurity atoms and repair lattice damage. The role of the Spacer is to block the subsequent source-drain injection and achieve self-alignment of the process.

Formation of NMOS and PMOS source drains

Injection of NMOS source drain: After the Spacer is fabricated, a thin layer of oxide is thermally grown as an injection barrier. A 7-lithography plate was used for the lithography of the NMOS source drain, followed by the implantation of high-energy As ions to form the source drain region of the NMOS.

Injection of PMOS source drain: After the photoresist is removed, lithography of the PMOS source drain is performed using an 8-lithographic plate. Next, the BF₂ ion is injected (BF₂ is a compound of B that is used to increase the doping concentration of PMOS source-drain) to form the source-drain region of PMOS. Due to the large mass of BF₂ ions, the injection energy is relatively low.

So far, the main steps of the 0.18μm CMOS front-end process have been completed, including the formation of the active region, the fabrication of N and P wells, the formation of gates, the formation of light doping source and drain, the fabrication of Spacer, and the formation of NMOS and PMOS source drains. Together, these steps form the basic structure of a CMOS integrated circuit and provide the basis for subsequent back-end processes (metal interconnects, etc.).

0.18μmCMOS Back End Aluminum interconnect process

In the back-end aluminum interconnection process, the main thing is the fabrication of metal interconnect, and the following are the detailed steps of 6-layer aluminum interconnection:

Making of Contact

Media deposition and planarization: First, a layer of TEOS (tetraethoxysilane) is deposited as the base media layer, followed by the deposition of TEOS (BPSG) doped with B and P to improve the fluidity and step coverage of the medium. Finally, a planarization process is carried out by CMP (Chemical Mechanical Polishing) to make the surface of the disc flatter.

Contact Hole Lithography & Corrosion: Contact holes are lithography using a specific lithography plate, and then dry etching is performed to remove the dielectric layer that is not covered by the photoresist to form the contact holes.

Contact hole filling: Ti (titanium), TiN (titanium nitride) and W (tungsten) are deposited, where Ti and TiN are used as the adhesion and barrier layers, and W is used as the filler material. The excess W on the surface is removed by the CMP of W, and only the W inside the contact hole is retained, forming the final contact hole structure.

The fabrication of the first layer of metal

Metal deposition: After the contact hole is fabricated, Ti, AlCu (aluminum-copper alloy) and TiN are deposited, with AlCu as the main conductive material, and Ti and TiN as the adhesion layer and barrier layer respectively.

First Layer Metal Lithography & Etching: Lithography is performed using a lithography plate of the first layer of metal, and then the metal layer that is not covered by the photoresist is removed by etching to form an interconnected structure of the first layer of metal.

Fabrication of through-holes and subsequent metal layers

Through-hole process: Through-holes are made in a similar process to contact holes and are used to connect circuits between different metal layers. Metal layer process: Starting from the second layer of metal, the production of each layer of metal includes metal deposits, photolithography, etching and other steps. As the number of metal layers increases, the thickness of the metal layer increases accordingly in order to withstand higher currents and provide better heat dissipation. Final Metal Layer and Section: After all the metal layers have been fabricated, the device is sliced and the disc is cut into individual chips.

Passivation and the making of Pads

Passivation layer deposition: After the top layer of metal is completed, SiO₂ and Si₃N₄ are deposited as passivation layers to protect the chip from damage from the external environment.

Pad Lithography and Corrosion: Lithography of the Pad is carried out using a specific lithography plate, and then the passivation layer on the Pad that needs to be led is removed by etching to form the lead Pad area.

0.18μmCMOS Back End Copper interconnect process

The main difference between the copper interconnect process and the aluminum interconnect process is the use of copper as the metal interconnect material and the use of a low-k dielectric as the isolation material between the metal layers. The following are the detailed steps of the copper interconnect process:

Pre-metal media deposition

Media deposition and planarization: First, undoped TEOS is deposited as the base media layer, followed by BPSG deposition and high-temperature densification and planarization. A further layer of undoped TEOS is then deposited as the final pre-metal dielectric layer.

Fabrication of contact holes

Contact Hole Lithography & Corrosion: Similar to the aluminum interconnect process, contact holes are lithographed using a specific lithography plate, and then the dielectric layer that is not covered by the photoresist is removed by corrosion.

Contact hole filling: A thin layer of Ti and TiN is deposited as an adhesion and barrier layer by CVD (Chemical Vapor Deposition) method, followed by the deposition of W for filling. The excess W on the surface is removed by the CMP of W, and the final contact pore structure is formed.

Fabrication of metal layer 1

Low-k dielectric deposition: Coating of low-k dielectric to reduce parasitic capacitance. Metal layer lithography and etching: SiO₂ is deposited as the end layer of the etching, and then metal 1 lithography and etching are carried out to form a metal 1-filled groove.

Copper Filling & CMP: Ta is deposited as an infiltrating layer of copper, and then the copper filling grooves are deposited using the CVD method. Excess copper on the surface is removed by CMP to form an interconnected structure of metal 1.

Fabrication of metal layer 2

Etch barrier and low k media deposition: SiN is deposited as the etch barrier layer, and then the low k media and SiO₂ are coated as the etching end layer and filler layer. Lithography and etching of through-holes and metal layers: Lithography and etching of through-hole 1 are carried out to form a through-hole structure. This is followed by photolithography and etching of metal 2 to form a pattern of metal 2.

Copper Filling & CMP: The Ta-infiltrated layer is deposited with PVD, followed by the groove is filled with CVD deposited copper. Excess copper on the surface is removed by CMP to form an interconnected structure of metal 2.

Fabrication of multi-layer metal interconnects and pads

Subsequent metal layer fabrication: The fabrication process of metal 3 and its upper layer is similar to that of metal 2, including the deposition of etching barrier layers, low-k media, SiO₂, lithography, etching, copper filling, and CMP.

Passivation and Pad fabrication: After the top metal layer is completed, Si₃N₄ and SiO₂ are deposited by PECVD method as the passivation protective layer of the device, and then the Pad is photolithography and corrosion treatment are carried out to form the lead Pad area.

Through the above steps, the whole manufacturing process of the 0.18μm CMOS back-end copper interconnection process was completed.