Summary of the evolution of semiconductor process technology from 180nm to 14nm

Summary of the evolution of semiconductor process technology from 180nm to 14nm

In the evolution of semiconductor processes from 180nm to 14nm, the differences in the structure of each layer are mainly reflected in device size, process technology, material selection and complexity.

Mask Layers

180nm-90nm: The number of lithography layers is about 20-30, mainly including the transistor gate, source-drain area, contact hole and metal interconnect layer (Metal 1-3).

65nm-45nm: Increase the number of layers to 30-40 layers, introduce shallow trench isolation (STI), stress engineering, and more metal layers (e.g., Metal 4-5).

28nm-14nm: The number of layers exceeds 50, and complex processes such as high-K metal gates (HKMG), self-aligning double patterns (SADP), and FinFET structures are added, and the metal layers are expanded to 7-10 layers.

Key layer technical differences

1)Gate

180nm-90nm：Polysilicon gate pole SiO₂ gate oxygen, gate length 180nm→90nm.

65nm-45nm：High K dielectric (such as HfO₂) replaces SiO₂ and reduces leakage current; Metal gates began to be introduced.

28nm：High K metal gates (HKMG) are fully applied to improve gate control capabilities.

14nm：FinFETs (fin field-effect transistors) replace planar structures, and the 3D gate significantly reduces the short channel effect.

Process nodes	Gate structure
180nm	Polysilicon gate + SiO₂ gate oxygen
90nm	Polysilicon gate + Thin SiO₂/SiON
65nm	High K medium (HfO₂) pilot
45nm	High K / Metal Gate (HKMG) transition
28nm	High K/Metal Gate (HKMG) is fully applied
14nm	FinFET (3D Fin Structure)

2)Isolation technology

180nm-90nm: Mainly local oxidation isolation (LOCOS), large size.

65nm and below: Shallow trench isolation (STI) has become mainstream, with better isolation and a smaller footprint.

Process nodes	Isolation technology
180nm	Local Oxidation Isolation (LOCOS)
90nm	Shallow Trench Isolation (STI)
65nm	STI Optimized
45nm	Strain silicon technology
28nm	Strain engineering optimization
14nm	STI size is miniature

3)Interconnect

180nm-90nm: Aluminum interconnect SiO₂ medium with fewer layers (typically 3-4 layers).

65nm-45nm: Copper interconnects fully replace aluminum, low-K media (such as SiOC) reduce parasitic capacitance, and metal layers increase to 5-6 layers.

28nm-14nm: Ultra-low K medium (k<2.5) and Damascus process optimized signal transmission with 7-10 metal layers.

Process nodes	Interconnect materials	Media material
180nm	Aluminum (Al) interconnect	SiO₂(k≈4.0)
90nm	Copper (Cu) interconnection pilot	SiO₂(k≈4.0)
65nm	Copper interconnect is fully applied	Low K media(k≈3.0-3.5)
45nm	Copper interconnect + low K media	Low K media(k≈2.7-3.0)
28nm	Copper interconnect + ultra-low K media	Super Low K media(k≈2.5)
14nm	Copper interconnect + ultra-low K media	Super Low K media(k<2.5)

4)Source/Drain

180nm-90nm: Lightly doped leakage (LDD) structure, formed by ion implantation.

65nm-45nm: Stress engineering (e.g., SiGe stress layer) improves carrier mobility.

28nm-14nm: Embedded SiGe (eSiGe) source-drainage and ultra-shallow junction technology further optimize performance.

Process nodes	Source leakage engineering
180nm	Light Doped Leak (LDD)
90nm	Shallow junction + stress engineering (SiGe strain)
65nm	Embedded SiGe(eSiGe)Source Drain
45nm	Super shallow knot(USJ) + NiSi silicide
28nm	raised S/D + High mobility channels
14nm	Fin Source Leak + Contact Optimization

Process complexity and new technologies

90nm-65nm：Immersion Lithography,improve Lithography resolution.

45nm-28nm：Dual patterning technology (DPT) solves the problem of lithography limits, and FinFETs are being developed at the 28nm node.

14nm：FinFET mass production, self-alignment quadruple pattern (SAQP) to achieve smaller line widths, EUV lithography technology began to be initially applied.

Process nodes	Patterning technology
180nm	Single-layer lithography
90nm	Single-layer lithography
65nm	Double exposure (DP) prototype
45nm	Self-Aligning Double Pattern (SADP)
28nm	Quadruple pattern (SAQP)/EUV pilot
14nm	EUV (Partial Tier) + SAQP

VI.Comparison of key process innovations

Process nodes	Core technology breakthrough	Representative craftsmanship	Material innovation
180nm	Standard CMOS process	Aluminum interconnect + LOCOS	SiO₂Grid oxygen
90nm	Strain Silicon + Immersive Lithography	Copper interconnect + STI	SiON Fence medium
65nm	High K / Metal Grating Pilot + Low K Media	Double exposure lithography	Hf Basis height K media
45nm	HKMG Comprehensive Application + Stress Engineering	SADP Patterning	The second generation of high K materials
28nm	Planar HKMG Extreme + 3D FinFET R&D	SAQP/EUV Pilot	Ultra-low K media(porous SiOCH)
14nm	FinFET Mass Production + EUV Lithography	3D device fabrication + high NA EUV	3rd generation high K material + strain engineering optimization

V. Typical application scenarios

180nm-90nm: consumer electronics, simple microcontrollers, analog circuits.

65nm-45nm: Smartphone baseband, mid-range processor, IoT chip. 28nm: high-performance computing, mobile devices (such as early Snapdragon, Kirin chips).

14nm: High-end processors (such as Intel Core, AMD Ryzen, Apple A9/A10), AI chips.