Short and Narrow Groove effects in the MOS process

Jan 22, 2026

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In deep submicron and nanoscale MOS processes, the short and narrow trench effects have a significant impact on the electrical characteristics of devices as key small-size effects, and their mechanisms and inhibition strategies need to be combined with device physics and process innovation.

Short furrow effect

When the length of the channel is close to the width of the depletion layer, the overlapping area under the gate increases, which reduces the gate voltage required to form a complete depletion zone.

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This effect is further exacerbated in Vds>Vgs-VT, because the concentration of the electric field at the drain may cause reliability problems such as the thermal carrier effect. In order to suppress the short ditch effect, the modern process adopts multiple strategies: shallow source leakage extension (SDE) combined with low-dose extension injection can reduce the width of the exhaustion zone, while halo injection (or pocket injection) effectively inhibits the widening of the depletion layer by forming a high doping zone at the edge of the channel, and realizes precise regulation of the threshold voltage.

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It is worth noting that the inverse short trench effect (RSCE) manifests as an abnormal increase in threshold voltage when the trench length decreases in some processes, which is usually attributed to channel doping non-uniformity due to lateral diffusion, which needs to be balanced by process optimization such as gradient control of halo injection.

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Narrow ditch effect

The narrow trench effect focuses on the influence mechanism of channel width on the threshold voltage. In the traditional LOCOS isolation process, the channel blocking dopant (such as p-type injection) at the edge of the field oxygen diffuses into the channel area during the high-temperature oxidation process, resulting in the widening of the gate edge exhaustion area, which requires additional gate pressure compensation, and finally increases the threshold voltage with the decrease of the channel width.

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The inverted doping trap process reduces the encroachment of the dopant at the edge of the gate by forming field oxygen after the trap is injected, but the bird's beak effect and the bending of the edge power line will still introduce a two-dimensional electric field distribution, resulting in an increase in the threshold voltage. With the popularization of STI technology, the narrow trench effect has taken on new characteristics: the inverse narrow trench effect (INWE) can occur when the trench width is very small (e.g., less than 0.2 μm), which is caused by the enhancement of the edge electric field at the acute angle of the top of the STI (reducing the surface barrier) and the fixed positive charge in the deposited oxide (pull-down effect on the nMOS threshold voltage).

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Currently, advanced processes have effectively mitigated the effects of INWE by optimizing STI filler materials (such as high-density plasma chemical vapor deposition oxides) and introducing edge rounding processes.

Recent research progress shows that 3D device structures (such as FinFETs and GAA nanosheets) enhance electrostatic integrity through multi-gate control, significantly suppressing the short and narrow trench effects. For example, FinFETs' three-dimensional channel structure allows for better gate control, while GAA devices further reduce the impact of short trench effects through a surround gate design. At the same time, the introduction of high-k dielectric and metal gate technology not only reduces the leakage of the gate but also improves the regulation ability of the gate to the channel, providing a new dimension for the stable control of the threshold voltage.

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In addition, machine learning-driven process optimization is being used to accurately predict and compensate for threshold voltage deviations caused by small-size effects, further expanding the process window. These innovations not only continue Moore's Law, but also provide a physical basis for the design of low-power, high-performance chips, reflecting the continuous value of collaborative innovation between process technology and device physics.

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