Second-level oxidation of Chip manufacturing: RTO rapid thermal oxidation

In the nanoworld of chip manufacturing, each oxide film is the cornerstone of transistor performance. When the process enters the sub-7nm node, the traditional furnace tube oxidation process faces obsolescence due to excessive heat budget and uneven thickness, while rapid thermal oxidation (RTO) technology has become a key process in high-end chip manufacturing due to its second-level response and atomic-level accuracy.

I. What is RTO?

Millisecond-level high-temperature oxidation art RTO (Rapid Thermal Oxidation) is a technology that realizes the growth of ultra-thin oxide layer in a very short time (1-10 seconds), and its core features are: heating rate: 50-150°C/s (traditional furnace tubes are only 5-10°C/min); Temperature range: 800-1100°C; Thickness control: 1-10 nm, accuracy up to ±0.01 nm.

Comparison with traditional furnace tube oxidation:

Parameters Conventional furnace tube oxidation RTO rapid thermal oxidation

Heating time 30-60Minutes 5-10Seconds

Heat Budget High (easy to lead to doping and spread) Very

Thickness uniformity ±2% ±0.5%

Interface defect density 10¹¹ cm⁻² 10¹⁰ cm⁻².

II. The core role of RTO: interface optimization

1. Perfect partner for high-k media: In the HKMG process below 28nm, RTOs grow SiO₂ layers at the interface of 0.5-1.2 nm to optimize the interface characteristics of HfO₂ and silicon; The equivalent oxide layer thickness (EOT) was reduced to 0.8 nm and the leakage current was reduced by 100 times.

The three-dimensional adaptability of FinFET achieves uniform oxidation on the three-dimensional surface of the fin (Fin) to avoid the "edge peroxidation" of traditional processes; In Intel's 14nm FinFET, the RTO controls the deviation of the top of the fin from the side wall oxide layer to <0.1 nm.

The thermal budget of the ultrashallow junction was controlled After injection in the source-drain extension zone, RTO activated the doped atoms at 1050°C/2 sec while suppressing the boron diffusion distance within 2 nm.

4. Defect repair of nanostructure Atomic oxygen (O*) fills the suspension bonds on the surface of silicon, reducing the interfacial state density to less than 10¹⁰ cm⁻² and increasing carrier mobility by 20%.

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III. Reaction mechanism of RTO

Reaction equation

Si(s) + O₂(g) → SiO₂(s) (Dry oxygen oxidation)
Si(s) + 2H₂O(g) → SiO₂(s) + 2H₂(g) (Wet oxygen oxidation)

Three-stage reaction process
1. Initial linear growth (0-2 nm)：
Oxygen molecules react directly with silicon, and the rate is controlled by surface reaction kinetics;

For every 100°C increase in temperature, the growth rate increases by 3 times.

Parabolic diffusion control (2-10 nm): oxygen atoms need to penetrate the formed SiO₂ layer, and the diffusion coefficient determines the rate;

Following the Deal-Grove model: thickness² ∝ time × diffusion coefficient.

3. Interface reconstruction (after oxidation): At 1070°C, silicon atoms are rearranged within 0.1 seconds to form a stress-free interface; the released hydrogen atoms passivate the remaining suspension bonds.

IV. The whole process of RTO process

Take the interface oxidation at the 5 nm node as an example:

1. Wafer pretreatment HF3H2O vapor cleaning to remove the primary oxide layer (thickness < 0.2 nm); Argon purge with cavity oxygen content < 1 ppm.

2. The rapidly heating tungsten halide array heats the wafer from 400°C to 900°C in 3 seconds; Real-time feedback on infrared temperature measurement on the back, temperature control accuracy ± 1°C.

3. Oxidation Reactions (Key Steps)

Parameter Set Value Function
Temperature 900°C balances growth rate with heat budget

Precise control of thickness0.8-1.2 nm
Oxygen flow ensures sufficient reactants
Control pressure to enhance gas adsorption
4. Rapid cooling
Cool down to 600°C within 0.5 seconds after cutting off the power supply;
Helium backcooling prevents wafer warping.
5. Quality inspection
Ellipsometer measurement thickness (accuracy ± 0.01 nm);