Poly-Si in Chip Making

Poly- Si

Polycrystalline silicon (Poly) is a non-monocrystalline silicon material composed of countless tiny silicon grains. Unlike monocrystalline silicon, such as silicon substrates, polycrystalline silicon typically has grain sizes between tens to hundreds of nanometers, with grain boundaries between grains.

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Synthesis method of polysilicon: LPCVD process

Low-pressure chemical vapor deposition is the mainstream technology for the preparation of polysilicon, the core of which is the thermal decomposition of silane (SiH₄) to form silicon atoms and deposit them into films.

SiH4→Si+2H2↑

Amorphous silicon is formed at low temperatures (<600°C) and polysilicon is formed at high temperatures (>600°C). The reaction chamber pressure is maintained at 0.1-1 Torr (low pressure environment improves film uniformity).

Synthesis of P-type and N-type polysilicon

The conductive type of polysilicon is achieved by doping, which is divided into P-type (boron-doped) and N-type (phosphorus/arsenic-doped), and the process methods include ion implantation and in-situ doping:

Ion implantation (mainstream technology)

N-type doping: injection of phosphorus (P⁺) or arsenic (As⁺), dose 1×10¹⁵–1×10¹⁶ cm⁻², energy 10-50 keV;

P-type doping: boron (B⁺) is injected at a dose similar to energy;

Annealing Activation: Rapid thermal annealing (RTA, 900-1000°C) repairs lattice damage and activates impurity atoms.

In-situ doping (synchronous doping in LPCVD)

Gas doping: mixing PH₃ (N-type) or B₂H₆ (P-type) in SiH₄ to directly deposit doped polysilicon;

Advantages: Injection damage is avoided, but doping uniformity control is difficult.

The central role of polysilicon in chip manufacturing‍‍‍‍

Transistor gate material

Polysilicon is deposited on a gate insulating medium→ doped→ etched and formed→ annealed at high temperatures. After doping, the resistivity is as low as 10⁻⁴ Ω·cm, and the control signal is transmitted. The work function is adjusted by N/P type doping (N-Poly for NMOS, P-Poly for PMOS).

Pattern transfer hard mask layer

When etching deep grooves or high aspect ratio structures, the hardness of polysilicon (6.5 on the Mohs scale) protects the underlying material. deposition of 500 nm polycrystalline silicon layers; Lithography defines the pattern; Dry etching of polysilicon (Cl₂/HBr plasma); Polysilicon is used as a mask to etch the underlying medium/metal.

Intermediate Process (MEOL) contact connection points

It forms a low-resistance contact between polysilicon and metals (e.g. tungsten, cobalt). Doped silicon is deposited in the contact pores as a transition layer between the metal and the silicon substrate to reduce the Schottky barrier; Connect adjacent devices with polysilicon in a shallow trench isolation (STI) area.

Conductive layer and work function control

In FinFETs, polysilicon is bound to a high-K medium such as HfO₂ to regulate the threshold voltage by doping type and concentration. The work function of N-type polysilicon ≈ 4.1 eV, matching the NMOS channel; The work function of P-type polysilicon is ≈ 5.2 eV, which is suitable for PMOS requirements.