Hybrid Bonding, Become A Chip Celebrity

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Hybrid Bonding, Become a "Chip" Celebrity

As Moore's Law gradually enters the second half of its development trajectory, the chip industry is increasingly relying on advanced packaging technology to drive leaps in performance. As packaging technology moves from flat to higher-dimensional 2.5D and 3D, interconnect technology becomes the key to the key. In the face of the increasing complexity and performance requirements of 3D packaging, traditional interconnect technologies such as wire bonding, flip chip bonding, and through-silicon via (TSV) bonding are increasingly revealing their limitations. Against this backdrop, hybrid bonding technology is becoming the new darling of the industry due to its revolutionary interconnect potential.

There are four main connected technologies

(Source: SK hynix)

Hybrid bonding, or Hybrid bonding, can be used in two main ways. The first is wafer-to-wafer, which is used in CIS and NAND, where hybrid bonding has proven its efficiency. Copper hybrid bonding first appeared in 2016, when Sony used this technology for CMOS image sensors; The other is die-to-wafer hybrid bonding, which is more difficult than wafer-to-wafer bonding, but this process change makes sense for logic and high-bandwidth memory (HBM).v

Wafer-to-Wafer (W2W) Hybrid Bonding Steps (Source: Applied Materials)

Die-to-Wafer (D2W) Hybrid Bonding Steps (Source: Applied Materials)

Hybrid bonding technology has the following features: 1) it allows different chip layers, such as memory layers and logic layers, to be directly interconnected without going through through-silicon vias (TSVs), significantly increasing signal transmission speed and reducing power consumption; 2) minimizes wire length through direct copper-to-copper bonding between the chip and wafer; 3) Compared to traditional TSV technology, hybrid bonding reduces the need for physical connections between layers, resulting in more compact chip designs and facilitating higher performance and density. It is reported that when hybrid bonding is applied, 10,000 to 100,000 through-holes can be connected in an area of 1 square millimeter; 4) Hybrid bonding also reduces mechanical stress inside the chip, improving the overall reliability of the product, while supporting higher data transfer speeds and lower energy consumption.

Hybrid bonding has become a key technology for chip building and future 3D packaging, and is one of the key technologies to achieve high-performance, high-density and low-power chip design. In this context, wafer fabs, storage fabs, and equipment factories are all eyeing hybrid bonding.

The pioneers of hybrid bonding

Hybrid bonding technology has become a consensus in the wafer manufacturing industry, with industry giants such as TSMC, Samsung, and Intel racing to advance the development of 5nm and more advanced process technologies. In this process, hybrid bonding technology is particularly critical and is seen as the only way to go for high-end manufacturing.

TSMC: The only company to commercialize hybrid bonding

In the field of hybrid bonding, TSMC, the world's No. 1 foundry company, has the most say. TSMC is the only chip company to date to commercialize hybrid bonding. TSMC's 3D package-SoIC is the hybrid bonding technology used, and the service called 3DFabric has been applied to AMD V-Cache. According to TSMC's public information, with innovative bonding solutions, SoIC technology provides strong bond pitch scalability for chip I/O, enabling high-density chip-to-chip interconnects. The bond pitch starts with a rule of less than 10 μm. Short chip-to-chip connections have a smaller form factor, higher bandwidth, better power integrity (PI), signal integrity (SI), and lower power consumption than the industry's most advanced packaging solutions today.

SoC-Exceptional-scalability Displayed by TSMC

(Source: TSMC)

TSMC's SoIC technology integrates homogeneous and heterogeneous chiplets into a single, SoC-like chip with a smaller footprint and thinner form factor that can be integrated holistically into advanced WLSI (aka CoWoS services and InFO). Visually, the newly integrated chip looks like a general-purpose SoC chip, but embeds the required heterogeneous integration functions.

Outlook Comparation of SoIC与SoC(Source:TSMC)

Samsung: Actively introducing hybrid bonding

Samsung Electronics is starting to introduce hybrid bonding in earnest, with Samsung's "one leg" to enhance its foundry capabilities and the other leg to power on HBM.

According to industry news on February 1, Besi Semiconductor and Applied Materials are installing hybrid bonding-related equipment at Samsung Electronics' Cheonan campus. Cheonan Campus is Samsung Electronics' advanced packaging production base. The device is expected to be used in next-generation packaging solutions such as X-Cube and SAINT. According to industry insiders: "As far as I know, the device is used for non-memory packaging. "

It is understood that Samsung Electronics' latest investment is mainly to strengthen its advanced packaging capabilities. Samsung Electronics is preparing to launch the X-Cube with hybrid bonding. The industry predicts that hybrid bonding can also be applied to the Saint platform, which Samsung Electronics plans to launch starting this year. The company plans to offer 3D packaging services such as Saint-S (stacking SRAM on logic chips), Saint-L (stacking logic chips on logic chips) and Saint-D (stacking DRAM chips on logic chips).

Industry predictions suggest that Samsung Electronics' investment in hybrid bonding facilities could win the hearts of major customers such as Nvidia and AMD. This is due to the increasing demand for hybrid bonding in the CoWoS packages used in the AI chips of these fabless customers. On the other hand, Samsung's HBM4 will launch in 2025, according to an editorial blog post published on the Samsung blog by SangJoon Hwang, executive vice president and head of the DRAM product and technology team at Samsung Electronics. The HBM4 memory will feature technologies optimized for high thermal performance, such as non-conductive film (NCF) assembly and hybrid copper bonding (HCB).

Intel: Hybrid bonding is on the horizon

At the 2022 IEDM conference, the 75th anniversary of transistors, Intel demonstrated its ambition to increase the density of packaging technology by 10 times using hybrid bonding technology. Intel plans to apply this technology to its 3D packaging technology, Foveros Direct, which was commercialized last year. At this year's ECTC, Intel published a paper on hybrid bonding technology. The technology on the left side of the diagram is called Foveros, with bumps spaced 50 microns apart and about 400 bumps per square millimeter. In the future, Intel aims to reduce bump pitch to about 10 microns and achieve 10,000 bumps per square millimeter.

The diagram below compares traditional bump bonding techniques with hybrid bonding techniques. Hybrid bonding technology reduces interconnect pitches to less than 10 microns compared to underfill, resulting in higher current-carrying capacity, denser copper interconnect density, and better thermal performance. However, hybrid bonding technology requires new methods of manufacturing, handling, cleaning, and testing.

According to reports, Intel is expected to be the first to adopt hybrid bonding technology between its logic chips and interconnectors in 2024. Foveros Direct is expected to employ a hybrid die-to-wafer bonding approach with a pitch expected to be between 9 and 10 microns. In comparison, Intel's Meteor Lake products have a pitch of 36 microns using hot compression bonding (TCB) technology, while Lakefield products have a pitch of 55 microns using bump joining technology via silicon vias (TSVs).

SK hynix: HBM is the first to introduce hybrid bonding

Storage manufacturer SK hynix is also eyeing hybrid bonding. Last year, SK hynix became a heavy profiteer of this round of AI boom by leading the way in high-bandwidth memory (HBM) chips. But what you may not know is that SK hynix is also well-known for packaging technology. For example, SK hynix's CoC (Chip on Chip) packaging technology can electrically connect two (or more) chips together without the need for TSVs (through-silicon vias). K hynix has also developed advanced packaging technologies such as heterogeneous integration and fan-out RDL technology. Last year, SK hynix maintained its position as the industry leader in HBM by taking the lead in introducing the large-scale reflow molding underfill (MR-MUF) process in the production of the fifth-generation HBM.

SK hynix's MR-MUF technology improves the quality of HBM's interconnects of more than 100,000 microbumps. In addition, the packaging technology maximizes the number of thermal virtual bumps and provides superior heat dissipation compared to the competition due to the use of a highly thermally conductive molded underfill (MUF) material. This advancement helped SK hynix increase its share of the HBM market and eventually take a leading position in the HBM3 segment.

Today, SK hynix is actively promoting the new "hybrid bonding" process in HBM chips to maintain its leading position in the global market. So why is HBM using hybrid bonding technology? First of all, let's familiarize ourselves with HBM chips, the so-called HBM, which is actually a memory that increases the speed of data processing by stacking the number of DRAM layers. It is mainly connected to the DRAM layer by means of TSV+ filler. According to SK hynix, HBM chips currently have a standard thickness of 720 micrometers (μm). "When the number of layers of HBM reaches 12 or more, there may be a problem with height, which needs to be solved by using hybrid bonding technology," Kang Ji-ho, head of wafer bonding at SK hynix, said at a conference. SK hynix expects that the sixth-generation HBM (HBM4), which will be mass-produced around 2026, will require up to 16 layers, posing a huge challenge to the existing packaging technology.

Hybrid bonding technology is the future of the HBM sector. To put it simply, if you think of HBM as a multi-storey building, each of which is tasked with storing data, when there are too many large floors, the traditional connection through through-silicon vias (TSV) + fillers alone is not enough to maintain its stability and reliability. Hybrid bonding technology is like applying a special "glue" between each layer, so that no additional supports are needed to hold the layers in place, and the thickness of the chip can be significantly reduced.

In short, with hybrid bonding technology, they were able to create high-level memory chips that were both efficient and small. Hybrid bonding is also known as the "dream packaging technology". SK hynix will continue to lead the development of HBM technology by announcing the application of hybrid bonding to HBM4 products this year, which will revolutionize the performance and power consumption of HBM4 products.

At present, SK hynix has made some progress. At the global semiconductor conference IEDM 2023 held in United States in December last year, SK hynix revealed that it has ensured the reliability of the hybrid bonding process used in HBM manufacturing. The company reported that its third-generation HBM product (HBM2E) uses 8-layer stacked DRAM and has successfully passed all reliability tests after adopting a hybrid bonding process. In this test, SK hynix evaluated the service life of HBM in a high-temperature environment and examined the potential problems that may arise during the customer's chip soldering process, covering four main aspects. Although this test was conducted on the third generation of the product, which is much lower than the HBM4 specification, it also demonstrates the potential of hybrid bonding.

HBM2E reliability test results using SK hynix hybrid bonding

SK hynix is reportedly expected to commercialize its hybrid bonding technology between 2025 and 2026. The latest Korea media news pointed out that SK hynix and TSMC recently jointly launched an alliance called "One Team Strategy", and the two will jointly develop the sixth generation of HBM (high bandwidth memory) chips, namely HBM4. In this collaboration, TSMC is expected to undertake the manufacturing of part of the HBM4 chip process, which may specifically include key packaging processes to enhance product compatibility and performance. In response, SK hynix said, "The company does not comment on the details of the alliance. "

Equipment manufacturers, the "shovel sellers" of hybrid bonding

Hybrid bonding technology is not an easy task. The main technical challenge was to achieve a defect-free copper-to-copper bond at an economical cost with almost zero chip-to-chip alignment error. This requires significant changes to upstream and downstream processes as well as equipment design. Integrated process development and co-optimization play a key role here. When performing hybrid bonding between chips or wafers, their surfaces must be kept to the highest level of cleanliness close to the atomic level, and the crucial step is to precisely align and bond the silica insulation to the copper contacts. This process requires extremely clean and high-precision bonding equipment. First, cleaning and plasma-activated equipment needs to be fully prepared for bonding. Immediately after, in the second stage, the integrated circuit is precisely placed onto the wafer using a bonding machine. Given the high-end precision requirements of these devices, they are relatively costly and comparable to the price of front-end manufacturing equipment. According to Besi's offer, the cost of each bonding device is between 2 million and 2.5 million euros.

In the hybrid bonding space, major equipment suppliers include Applied Materials, KLA Tencor, Lam Research, ASM Pacific Technology (ASMPT), and BE Semiconductor Industries (BESI). Just as shovels and screens were critical to gold diggers in the gold rush era, hybrid bonding equipment is an essential tool for chipmakers to achieve technological breakthroughs. The accuracy, reliability, and innovation of their equipment are directly related to whether chipmakers can win in the fierce market competition.

Thanks to long-standing relationships with Intel and TSMC, Netherlands back-end specialist Besi is currently well-positioned in the field of chip-to-wafer hybrid bonding. According to its CEO, Brickman, eight years ago, Semiconductor Manufacturing Company asked Besi to start developing bonders for its technology. "TSMC has helped us throughout the learning curve," he said in an interview with Pierre Ferragu of New Street Research last year. "We are in a unique situation with the right customers. We've been picking winners since the beginning. Collaboration with Applied Materials has been extremely helpful in understanding the requirements of a cleanroom environment. "

BESI and Applied Materials work closely together in the field of hybrid bonding. Since October 2020, Besi and Applied have been developing their technology by establishing a Center of Excellence (CoE) in Singapore. Looking at the hybrid bonding portfolios of both companies, Besi is focused on mass production of hybrid bonding die attach equipment, while Applied manufactures a wide range of equipment from dielectric deposition equipment to plasma equipment and chemical mechanical polishing (CMP) equipment. Applied's Insepra SiCN and Catalyst CMP systems enable state-of-the-art hybrid bonding and enhanced surface treatments with new materials. As mentioned earlier, Samsung's production line is also the result of the joint efforts of Besi and Applied Materials. According to Besi, the total cost of building a cleaning and bonding line is around 5 million to 6 million euros. Applied Materials and Besi each account for half of this, depending on the application – memory or logic chips.2021年,在COVID危机期间的半导体热潮中,Besi announced that both Intel and TSMC have committed to the purchase of 50 hybrid bonders. Orders really start to grow in 2023, so those plans seem to be delayed somewhat, but Besi says it already has the capacity to produce 180 hybrid bonders per year. If this capacity is fully utilized, it will mean an additional 400 million euros in sales.

The EV Group in Austria has been supplying for many years a plasma-activated system for cleaning chips and wafers and preparing the system for placement. EVG has partnered with ASM Pacific, which provides bonders. EVG has proven itself in the hybrid wafer-to-wafer bonding market, leading the way in this market with hundreds of machines. Sensors in almost all mobile phones go through a wafer-to-wafer process with EVG devices. In the high-end CMOS sensor market, EVG is competing with Japan's TEL.

来源：EV Group