Formation of Flow-Fin in FinFet Process

The evolution of FinFETs (FinFETs) from planar transistors to FinFETs is an advanced transistor architecture designed to improve the performance and efficiency of integrated circuits. It reduces the short-channel effect by converting traditional planar transistors into three-dimensional structures, allowing for smaller, faster, and less power-consuming transistors. In this article, we will introduce the FinFET manufacturing process, starting with the silicon substrate and ending with the fabrication of the fin.

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1. Initial preparation and surface treatment

Wafer cleaning
Before any processing begins, silicon wafers must undergo a thorough cleaning process to ensure that their surface is free of impurities or contaminants. This step is critical to obtaining high-quality FinFET devices.

Pad oxide layer growth. Next, a very thin layer of silicon dioxide (SiO2) is thermally grown on the silicon surface to act as a pad oxide layer. This layer not only protects the silicon substrate from subsequent processing, but also provides a good interface for subsequent silicon nitride deposition.

Silicon nitride deposition
Subsequently, a layer of silicon nitride (SiN) is deposited on top of the pad oxide layer by chemical vapor deposition (CVD) or other methods. Silicon nitride plays a dual role here: it acts both as a hard mask (HM) to guide silicon etching to form fins; It also acts as a CMP (Chemical Mechanical Polishing) stop layer to ensure that the STI oxide planarization process does not over-erode the underlying material.

2. Application of SADP technology

Since the fin spacing is so small at advanced nodes such as 22 nm or 14 nm, a single 193 nm immersion lithography cannot achieve the required level of fineness, so self-aligning double patterning (SADP) technology was introduced to increase the pattern density.
SADP false pattern layer deposition
First, a layer of temporary material (e.g., amorphous silicon a-Si) is deposited on top of the silicon nitride hard mask to act as a "fake" pattern layer. The material needs to have highly selective etching properties to distinguish it from the underlying silicon nitride and sidewall spacer materials in subsequent steps.
Photoresist application and exposure
A uniform layer of photoresist is applied over the entire stacked structure and exposed using a specific line-space pattern mask to define the approximate position of the fins. This pattern will be the foreshadowing of the etching process that will be referred to.
The pattern is transferred to the false pattern layer
The exposed photoresist is developed to form the initial "fake" pattern of the fin. These patterns are then transferred to the underlying amorphous silicon layer by plasma etching until they reach the silicon nitride surface.

Remove the photoresist
Once etching is complete, the photoresist must be removed, usually consisting of stripping and cleaning steps to prepare for the next step. This step ensures that there are no residues that affect the subsequent process.
Conformal spacer deposition

Use ALD to deposit a conformal dielectric layer (e.g., SiOx) that evenly covers all surfaces, which will form a sidewall spacer in a subsequent etching retreat step. The choice of this layer is crucial to the final shape of the fins.

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Etching backs to form a spacer
Anisotropic dry etching is performed on the conformal dielectric layer, leaving only the dielectric layer on the sidewall perpendicular to the wafer surface, resulting in the formation of a spacer. These spacers eventually become patterned templates for the actual fins. If amorphous silicon is used as a false patterning material, a KOH solution can be used to remove the amorphous silicon with little to no impact on the silicon oxide spacer or the silicon nitride hard mask underneath.
Remove the fake pattern
Use highly selective etchants to remove amorphous silicon false patterns without damaging the silicon oxide spacer or the silicon nitride hard mask underneath. This leaves a photolithography of the double-density spacer pattern, which corresponds to the fins that follow.

3. The fin pattern is refined

Cutting mask application

The photoresist is coated again and photoetched with the aim of defining which areas will be retained as fins and which areas need to be removed. This step determines the exact layout of the fins.

Spacer patterning
Using reactive plasma etching technology, unwanted spacers are selectively removed while minimizing the impact on silicon nitride hard masks.

Fins are eclipsed for a moment
The remaining spacer is used as a mask for the primary silicon etching step. This step directly determines the shape and size of the fins, so the etching parameters must be tightly controlled to obtain the ideal fin structure. During the etching process, the pad oxide is first removed, and then the silicon fins are etched according to the pattern of the silicon nitride hard mask. For 14nm process chips, the minimum fin pitch can be as small as 42nm.

These steps form part of a typical FinFET process flow from silicon substrate to Fin formation. The entire process involves multiple sophisticated engineering and technical challenges aimed at achieving high-performance, low-power integrated circuits. As technology advances, FinFET processes are evolving to accommodate smaller feature sizes and higher levels of integration. Each step is carefully designed to ensure the optimal quality and performance of the final product.