Intel's Senior CPU Architect Started A New RISC-V Startup

Intel's Senior CPU Architect Started a New RISC-V Startup

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Take core founder Debbie Marr, for example, who was an Intel Fellow and Chief Architect of the Advanced Architecture Development Group (AADG) and has been with Intel for 33 years.

A group of Intel's senior CPU architects recently left the company to form a RISC-V startup called AheadComputing. The architects, who have a combined more than 80 years of experience at Intel, come as the company announced thousands of layoffs.
Co-founded by Debbie Marr, Mark Dechene, Jonathan Pearce, and Srikanth Srinivasan, AheadComputing is "dedicated to designing, validating, and licensing compelling RISC-V core IP." The company was officially launched on July 18, weeks before Intel's layoffs were announced. At present, AheadComputing's official website is simple, containing only the company's mission, founder profile, a founding announcement, and recruitment information, mainly recruiting talents with experience in CPU design and verification. The most notable aspect of AheadComputing is the extensive experience of its founding team: Debbie Marr, a former Intel Fellow and Chief Architect of the Advanced Architecture Development Group (AADG), has been with Intel for 33 years. She has been instrumental in the development and promotion of Intel's Hyperthreading technology and holds more than 40 patents. Mark Dechene: Former principal engineer and CPU architect at Intel, he worked at Intel for 16 years. He has been involved in the architecture development of several CPU products such as Haswell, Broadwell, Goldmont, Goldmont Plus, Tremont, and Skymont, and holds more than 15 patents. Jonathan Pearce: Former Chief Engineer, CPU Architect, and CSP and Strategist at Intel Advanced Architecture Development Group, he spent 22 years at Intel. He has been involved in the development of multiple generations of Intel Core SOCs and holds 19 patents. Srikanth Srinivasan: Over 20 years of technical leadership experience in product development. During his time at Intel, he was involved in the design of well-known chips such as Nehalem, Haswell, and Broadwell, and led the front-end and back-end CPU teams of the Advanced Architecture Development Group. He has more than 12 highly cited papers and 50 patents. The establishment of AheadComputing has sparked concern in the industry and raised concerns about Intel's future. Intel's recently announced layoffs are the largest in its 56-year history, while also facing disruptions to construction plans and brain drain that could impact Intel's recovery.

The rapid development of AI technology has put forward unprecedented requirements for chip computing power. With its unique advantages, RISC-V shows great potential in AI applications. Some small AI models are able to realize the full potential of RISC-V. Compared to traditional ARM and x86 instruction sets, RISC-V has a cleaner design and is easier to update and expand. For example, you may have downloaded ARM documentation, and thousands of pages of it can be laborious to read, let alone revise. RISC-V does not have this problem, and anyone can obtain the source code of RISC-V according to their own needs, customize and optimize it, without paying high licensing fees. For example, small AI models in IoT devices. Taking ChatGPT as an example, this kind of large-scale AI model training requires a lot of computing power and resources, and edge AI devices cannot carry such high computing power requirements. However, for some smaller AI models, RISC-V can well meet their computing power needs, especially in IoT devices, RISC-V has shown great advantages. In this regard, RISC-V has become the first choice of some AI chip design companies due to its scalability and low cost. For example, Samsung SAIT has set up an advanced processor lab in Silicon Valley to design RISC-V-based AI chips, with the goal of disrupting the existing market pattern. In the field of consumer electronics, Alibaba's Damo Academy announced that a new iteration of the Xuantie processor family will have matrix computing expansion functions to enhance AI computing capabilities. This opens up more options for the future of AI computing. ESWIN Computing's RISC-V edge computing AI chip has powerful video encoding and decoding capabilities to meet the needs of a variety of application scenarios. In the field of robotics, AGTech has launched a RISC-V-based SLAM mapping and obstacle avoidance navigation trolley, which is the first time that RISC-V has been applied to the field of ROS robots, demonstrating the unlimited potential of RISC-V in the field of AI.

The world's first domestic Nanhu CPU RISC-V notebook was released At the 2024 RISC-V China Summit held recently, Shenzhen Qunxin Shining Technology Co., Ltd. released the world's first Xiangshan notebook - Ruyi Xiangshanben. According to reports, Ruyi Xiangshan is led by the Institute of Software of the Chinese Academy of Sciences, and Qunxin Shining Technology, Yingqi Intelligence, and Beijing Kaixin Institute jointly participate in the research and development, and it is the world's first notebook equipped with Xiangshan Nanhu processor. In terms of configuration, Ruyi Xiangshan uses a 14-inch high-definition LCD screen, equipped with a maximum 2.5GHz Xiangshan Nanhu processor, equipped with 8GB DDR5, integrated AMD RX550 independent graphics, and supports dual-screen different graphics. In terms of interfaces, the laptop offers two high-speed USB3 ports, two 2.5Gbps Ethernet ports, and a trackpad that supports 9 gestures. It is understood that Xiangshan is currently the highest-performing open source RISC-V processor core in the world, and the development goal of "two cores" of Xiangshan classic core and Xiangshan high-performance core has been determined. The classic core is based on the second-generation Xiangshan engineering optimization, benchmarks against the ARM A76, and provides CPU IP cores for pan-industrial fields such as industrial control, automotive, and communications. The high-performance cores are based on the third-generation Xiangshan (Kunming Lake) performance improvement, benchmarked against ARM N2, and provide high-performance CPU IP cores for data centers and computing facilities.

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