TSV Process

TSV Process Overview

2.5D/3D packaging technology, as the current cutting-edge advanced packaging technology, has a wide variety of solutions, and will dynamically adjust according to different application needs and technology development, covering chip thinning, chip bonding, wire bonding, flip bonding, TSV, plastic packaging, substrate, lead frame, carrier tape, wafer-level thin film process and other types. Some processes need to be further developed according to the specific requirements of 2.5D/3D packaging, such as wire bonding technology in 3D packaging, which has higher standards for wire arc height and solder joint size, which requires process improvement and innovation. In addition to the TSV process, this book has introduced most related technologies, and due to space limitations, this chapter only focuses on the TSV process technology.

Compared with wire bonding, TSV can significantly shorten the length of interconnect wires, reduce signal transmission delay and loss, increase signal transmission speed and bandwidth, reduce power consumption and reduce package size, and is one of the effective means to achieve multifunctional, high-performance, high reliability, and lighter, thinner, and smaller system-in-packages. As the core technology of 2.5D/3D packaging, TSV is different from other 3D packaging that uses intermediaries such as substrates and film wiring, and the chips are connected by conductive vias and solder bonds, with less thermal mismatch and shorter interconnect length.

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TSV's excellent 3D packaging performance and huge development potential are called the fourth generation packaging technology. In the mid-80s of the 20th century, the concept of filling conductors in vertical TSVs was clearly proposed, although it was not yet realized at that time. In the mid-90s of the 20th century, Bosch developed deep reactive ion etching (DRIE) technology, which made it possible to etch vertical deep holes on silicon wafers. At the end of the 20th century, high depth ratio TSV filled with tungsten or polysilicon conductors was successfully achieved. Since 2000, electroplating copper in deep holes has gradually become the main way to fill high abyss ratio TSV. Since then, advances in wafer bonding, bump manufacturing, wafer thinning, and chemical-mechanical polishing have further promoted the improvement of TSV packaging technology.

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TSV process

TSV technology is essentially a wafer-level process, so its production can be integrated into different aspects of the integrated circuit manufacturing process, which can be divided into four types: front front first via, front middle via, front rear via, and back back via.

Front-facing vias refer to drilling holes in the active circuit surface of the wafer. Front-front via technology is the formation of vias on the initial silicon substrate, that is, the through-hole fabrication is completed before the active layer of the chip front-end manufacturing process is formed, and the TSV fabrication can be carried out before the metal interconnect process at the front end of the wafer fab. The significant advantage of this solution is that it does not need to change the process and design of existing integrated circuits, and can also reduce the cost of seed layer deposition, shorten plating time and increase production capacity, and some manufacturers have adopted this technology in the field of high-end Flash and DRAM. When TSV holes are made between CMOS and the back end of line (BEOL), they are called front-middle vias, where BEOL refers to the back-end process of chip manufacturing, which begins with the first layer of metal interconnect after the completion of a single device and is completed in the wafer fab. Backside post-through-hole technology is drilled on the back side after a chip or wafer is bonded to another wafer.

The process of TSV production is as follows: (1) drill deep holes on the silicon wafer to exceed the target thickness of TSV; (2) sedimentary medium layer; (3) Deposition of barrier layers, adhesion layers and seed metal layers on the surface of silicon wafers and deep pores; (4) Fill the deep hole by electroplating copper or other conductive materials; (5) Use chemical mechanical polishing to achieve surface flattening and remove excess seed metal layer; (6) The copper layer or through-hole conductive layer is exposed by grinding or etching.

Key processes for TSV technology

The key processes of TSV include wafer thinning, through-hole fabrication, and bonding.

1. Thinning

The TSV process has strict requirements for wafer thickness, which needs to be controlled within 75μm; With the increase of TSV package density and the reduction of aperture size, the wafer thickness is still decreasing, so wafer thinning has become one of the key links of the TSV process. The thinning process of traditional packaging usually only needs to reduce the wafer to 200~350μm, and special packaging only needs to be reduced to 150~180μm, at which time the silicon wafer is still thick enough to withstand the damage and internal stress caused by grinding during the thinning process, and its own rigidity is easy to transport. However, the TSV process requires wafer thinning to less than 50μm, and how to reduce thinning damage and achieve stable transport of flexible wafers has become a new challenge. In the traditional thinning process, the surface damage left after rough grinding and fine grinding is the main cause of silicon wafer breakage - grinding is a physically damaging process that removes silicon material through physical pressure, damage, cracking and removal processes. In order to eliminate such surface damage and stress, the industry has tried various methods such as dry polishing, wet polishing, dry etching, and wet etching. At present, the mainstream solution in the industry is to use integrated equipment, which integrates the grinding, polishing, protective film removal and dicing film pasting of silicon wafers in the same equipment, and the whole process of silicon wafers from grinding to pasting the dicing film is adsorbed on the vacuum suction cup through the mechanical conveying system, and it is always kept in a flat state. When the silicon wafer is pasted on the dicing film, even if the thickness is thinner than the dicing film, it will remain flat according to the shape of the film and will no longer warp or sag, thus solving the transportation problem.

2. Through hole

1) Drill

Wafer drilling is the core part of the TSV process, and currently uses two main methods: dry etching (also known as Bosch etching) and laser etching. Originally developed for MEMS technology, the Bosch etching process is characterized by rapid alternating silicon removal (using SF₆ plasma etching) and sidewall passivation (using CF₄ plasma deposition). The cold etching rate can reach 50μm/min, the aspect ratio can reach 1:80, and the accuracy is sub-micron.

Laser etching eliminates the need for masks, eliminating the need for photoresist coating, exposure, development, and degumming. South Korea's Samsung has applied this technology to memory stacking. The aspect ratio of laser etching is about 7:1, which is weaker than dry etching, and is more suitable for scenarios with a small number of vias on the chip. If the number of through-holes exceeds 10,000, the efficiency of using lithography combined with dry etching is higher. In addition, when the through-hole size is reduced to less than 10 μm, it is still challenging to further reduce the hole size with laser drilling.

2) Through hole insulation

Through-hole insulation is usually deposited by the CVD process with an oxide (SiO₂) insulation layer and silane or TEOS as the raw material. If TSV insulation and filling are carried out after the chip circuit is manufactured, the appropriate deposition temperature should be selected to avoid affecting the completed circuit parts. The typical temperature of TEOS deposition is 275~350°C, and a functional insulation layer with suitable performance can be obtained. For applications such as CMOS image sensors and memory, lower deposition temperatures are required. At present, some equipment manufacturers have developed low-temperature oxide deposition technology to deposit thin films at room temperature as a highly efficient organic insulating layer for TSV.

3) Barrier layer, seed layer and filler

In the through-hole copper process, the TiN adhesion/barrier layer and the copper seed layer are typically deposited by sputtering. However, for through holes with a depth-to-width ratio greater than 4:1, the step coverage effect of traditional PVD DC magnetron technology is not good, while PVD technology based on ionized metal plasma (IMP) can achieve uniform deposition of the side wall of the hole and the bottom copper seed layer. Due to the low cost of electroplated copper, the through holes are usually filled with electroplated copper after the seed layer is deposited. However, during TSV plating, the orifice will gather more power lines due to the tip effect, resulting in a much higher current density than in the hole. Without additives, the orifice deposition rate will be much faster than that in the hole, and the copper ion exchange in the well is difficult, and it is easy to fill the orifice and not completely deposit in the hole. Therefore, it is necessary to adjust the plating deposition rate of the bottom, side wall and surface of the hole by additives (inhibiting orifice deposition and enhancing bottom deposition), or using periodic reverse pulsed current plating to achieve complete filling of the through hole. Hollow copper filling takes a long time and reduces production efficiency, which is a problem faced by TSV copper filling.

3. TSV bonding

The process used in TSV bonding includes intermetallic bonding technology and polymer bonding bonding. The core goal of bonding is to form stable mechanical connections, electrical connections, and thermal conduction channels between chips or components, integrating the originally separate chips and components into a complete packaged product.

From the perspective of the characteristics of the bonding process, intermetallic bonding is mainly divided into two categories: thermocompression bonding and eutectic bonding. For example, copper-copper bonding uses hot pressing bonding, while copper-tin, gold-tin, etc. bonding belongs to eutectic bonding. The principle of copper-copper hot press bonding is: in a vacuum environment or a protective atmosphere, apply high temperature and high pressure to the two closely bonded copper surfaces, and maintain it for a long enough time so that the copper atoms on the two bonding surfaces are fully diffused, and finally fuse into a whole, so as to achieve bonding. However, this bonding method is time-consuming and requires more stringent process conditions.

In recent years, low-temperature metal bonding has become a research hotspot in the field of packaging. The researchers hope to find a bonding method that can form good electrical and mechanical bonds at lower temperatures, and the reaction products can withstand high temperatures. Copper-tin bonding is preferred due to its excellent electrical and thermal properties, as well as its low bonding temperature (tin's melting point is 232°C). During the copper-tin eutectic bonding process, the metal tin melts to form a liquid state at low temperature, which promotes full contact between copper and tin, accelerates the diffusion between the two, and rapidly generates metastable high melting point intermetallic compounds Cu₆Sn₅ (melting point 415°C) and stable compound Cu₃Sn (melting point 676°C), and then completes the bonding. This bonding method can effectively prevent the bonded part from melting due to heat during the subsequent bonding process when stacking multiple layers, which is crucial for the reliability of 3D packaging. In addition, due to the good deformation ability of tin solder, copper-tin bonding does not require high flatness and cleanliness of the bonding surface, even if there are certain undulations or tiny particles on the surface, a good bond can be formed. At the same time, liquid tin can speed up the diffusion between copper and tin, making the bonding efficiency higher. As interconnect density increases, the latest developments in hybrid bonding technology may also become an important choice.

TSV application development

TSV technology enables 2.5D and 3D packaging, which offer significant advantages in terms of package density and interconnect length in current 3D packaging solutions. Therefore, the application progress of TSV reflects the cutting-edge development trend in the field of 3D packaging to a certain extent.

1. CMOS Image Sensor

In 2006, Toshiba Corporation launched the world's first product with integrated TSV technology, the CMOS Image Sensor (CIS), and mass production was achieved in 2007. Performance improvement and miniaturization are the core driving forces behind the development of the CIS. The development of 3D CMOS image sensors equipped with TSV has successively gone through the stages of front-side imaging (FSI), backside imaging (BSI), and then hybrid 3D stacked BSI. Currently, CIS is the largest application market for TSV technology.

2. MEMS field applications

At the end of the 20th century, deep ion etching technology began to be applied to MEMS for the manufacture of polysilicon TSVs (such as those used in microcantilever beams and micromechanical ultrasonic transducer arrays), as well as monocrystalline silicon TSVs (such as silica trench isolation structures in microengines). In the 21st century, many MEMS manufacturers and foundries have commercialized inertial sensor products and related manufacturing services, including air-gapped silicon TSVs for wafer-level vacuum packaging (WLVP). At the same time, thin-film acoustic resonators (FBARs) using hollow metal TSV and WLVP technology have also been commercialized and widely used in wireless communications. The integration of TSV and WLVP technology into MEMS can reduce the package size and cost to 1/10 to 1/5 of the original price, which has greatly accelerated the adoption of MEMS in consumer and mobile electronics in the past decade. In 2014, Bosch developed and launched an integrated MEMS sensor based on front-facing mid-through-hole TSV, which uses a TSV of 10 μm × 100 μm through-hole (10:1 diameter ratio), which is made of copper electroplating, which significantly reduces the surface area and thickness of the package compared to other mainstream MEMS TSV integrated packaging solutions. At present, MEMS has become an important application field of TSV technology.

3. Memory field applications

TSV technology can effectively increase memory capacity and bandwidth - with high-density TSV vertical interconnect technology, stacking multiple chips can significantly enhance memory capacity and performance. Major memory manufacturers have adopted TSV 3D stacking technology to develop related products. In 2009, Samsung launched 8Gb 3D DDR3 DRAM based on TSV 3D packaging, which reduces standby power consumption by 50% and 25% respectively, and increases I/O rates to more than 1600Mb/s through 300 TSVs. In 2014, the company released 16Gb 3D DDR4 SDRAM with TSV technology, with an I/O rate of 2.4Gb/s and a stack of 4 chips.

TSV technology also has important applications in high-bandwidth memory (HBM). The HBM stack is not physically integrated with the CPU or GPU, but is interconnected via a small-pitch high-density TSV adapter board. HBM has faster speed and higher bandwidth due to its characteristics close to chip-integrated RAM, making it suitable for scenarios with high memory bandwidth demands. In high-performance CPU/GPU applications, 2.5D TSV adapter boards play a key role as a platform-based technology. Memory, especially HBM products, has greatly increased bandwidth thanks to TSV technology. In 2014, Hynix released 1.2V 8Gb 8-channel high-bandwidth memory stacked DRAM with a bandwidth of 128GB/s using 29nm process and TSV technology. At present, memory is one of the main application markets for TSV technology.

Samsung 3D DDR4 DRAM package

4. Application in other fields

Power electronics, analog electronics and communications are also important application positions of TSV technology. In 2021, the Fengjuan Wang team from Xian University of Technology, Xidian University and the University of Manchester proposed and developed three five-order ultra-small hairpin bandpass filters based on TSV technology for 6G mobile communication needs.

TSV Technology Outlook
As TSV technology continues to evolve, the through-hole size continues to shrink, and the thickness of each layer of chips in the stackup will also be further reduced. Studies have shown that when the wafer thickness is reduced to less than 5 μm, the circuit performance will not be significantly degraded. It is foreseeable that in the next ten years, the development of traditional devices will gradually touch their own physical limits, and the difficulty of subsequent breakthroughs may increase significantly; However, new devices such as one-dimensional material devices are still in the laboratory stage and are difficult to achieve large-scale commercialization. Therefore, continuous improvement of integration at the packaging level has become the key at present, and through-silicon via technology will continue to be a research hotspot in the microelectronics industry in the next few years. The demand for TSV in rapidly developing chip applications such as memory, logic circuits, and CMOS image sensors will continue to promote the improvement and upgrading of this technology.

In addition, TSV technology can also achieve heterogeneous integration of different types of chips - for example, mobile phone power amplifiers mostly use GaAs technology, through which GaAs circuits can be bonded to CMOS circuits to form a complete functional circuit. However, while developing rapidly, 3D packaging still faces many challenges, and issues such as reliability, heat dissipation, material matching, and chip testing still need to be thoroughly studied to promote the commercialization of through-silicon via technology.