Chip Failure Mechanisms: An Introduction to NBTI

NBTI stands for Negative Bias Temperature Instability. It refers to the reliability problem in which a PMOS device operated under negative gate bias and elevated temperature exhibits a time-dependent drift in threshold voltage, transconductance, saturation current, and other parameters. During normal PMOS conduction the gate voltage is negative; this negative bias forms a hole inversion layer in the channel and accumulates holes at the Si/SiO₂ interface, while high temperature accelerates interface reactions and hydrogen diffusion. NBTI is not an instantaneous breakdown but a gradual, cumulative degradation of parameters under stress. NMOS has its counterpart, PBTI (Positive Bias Temperature Instability), but the two rest on different physical premises. What NBTI changes is how strongly the device drives current - not whether the device turns on at all.

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How Interface Degradation Occurs

Under negative gate bias and elevated temperature, hole trapping, Si–H bond breaking, and dielectric defect generation take place simultaneously near the interface. Holes in the inversion channel interact with Si–H and Si–O bonds: Si–H bonds break and release hydrogen, which diffuses through the oxide and creates oxide traps; trapped holes give rise to positive charge; prolonged stress also generates new defects inside the dielectric. The reaction–diffusion picture describes this as Si–H bond breaking, hydrogen release and diffusion, and subsequent trap formation. The three mechanisms have different time constants: hole trapping is relatively fast and partially recoverable, whereas interface-state generation and new bulk dielectric defects are slower and include a long-term, non-recoverable component.

Device Parameter Shifts and System-Level Impact

At the device level, degradation appears as an increase in the absolute value of threshold voltage, a drop in saturation current, a loss of transconductance, and a rightward shift of the transfer curve. At the circuit level, it appears as increased delay and a reduced maximum operating frequency. Maintaining performance then requires a higher supply voltage; since dynamic power scales with the square of voltage, and leakage adds on top of that, the resulting power increase raises heat dissipation and junction temperature - which in turn accelerates NBTI, forming a positive feedback loop. The impact of NBTI therefore propagates from device parameters to circuit timing, functional stability, and system power. Mismatch-sensitive circuits such as SRAM are also affected through threshold-voltage mismatch. In scaled devices the supply voltage has not decreased in proportion to feature size, so electric-field stress grows and the problem becomes more pronounced.

Recovery Effects and Lifetime Evaluation

After the stress is removed, the device partially recovers: the longer the measurement delay, the smaller the read-out threshold-voltage drift. Degradation under AC operation is generally lower than in DC stress tests, yet no universal model links DC and AC behavior. Recovery originates from hydrogen-related kinetics, with fast and slow recovery coexisting, and permanent damage remains. NBTI testing is mostly performed on test structures under DC bias, so the extracted lifetime is more appropriate as a figure of merit for process comparison. In engineering practice, lifetime is evaluated through accelerated stress tests at multiple temperatures and voltages followed by extrapolation; a common criterion is that the threshold-voltage drift after 10 years must not exceed 0.1 V. If short-term tests fail to account for recovery effects, they will underestimate long-term risk.

Process- and Design-Level Mitigation

On the process side, pre-gate cleaning, gate dielectric growth, nitridation, high-k deposition, implantation, plasma steps, annealing, and hydrogen/fluorine passivation all affect interface quality and trap density. Nitrogen increases the dielectric density, but excess nitrogen near the interface degrades passivation. Hydrogen passivation lowers the initial interface-state density, yet it can depassivate under stress. Fluorine forms more stable bonds, but its dose and distribution must be controlled. SiON and HKMG stacks differ in where the dominant defects reside. On the design side, options include HVT or multi-Vt devices, reducing PMOS gate bias and stress duty cycle, DVFS, transistor stacking, and establishing NBTI monitoring and reliability verification. The goal is not to eliminate degradation, but to push the degradation rate within the lifetime requirement.